US5396170A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single chip IC tester architecture
Assignee: Cadence Design Systems Inc
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Filing: 1993-06-01
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Granted: 1995-03-07
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Expires: 2013-06-01
Abstract
Abstract An integrated circuit (IC) test architecture and technique which can be used in conformity with the IEEE 1149.1 test standard and configured on a single chip. This chip can be remotely controlled via a PC or workstation to generate stimulus and collect response data to fully test an IC which matches the foot print of the test chip. The specified technique uses the IEEE test standard with additional logic on a single chip which permits at speed test functional test of ICs. The test chip can be connected to a PC or workstation via the four (4) channel Test Access Port. By remotely controlling the test chip from the PC or Workstation, stimulus and response data can be generated to completely test any Integrated circuit having a foot print matching the IC of the test chip. In one embodiment, the test chip is mounted on a probe card for at speed functional test of wafers. In another embodiment, the test chip is placed in a socket or adapter for at speed package level test. In another embodiment, the test chip is sandwiched between a device under test (DUT) and the PCB on which the DUT is mounted for at speed board test.
Inventors
- 👤 Daniel D'Souza
- 👤 Ruth Alexander
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:07
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3187; G01R31/3185; G01R31/318533; G01R31/318577; G01R31/31858; G01R31/318552; G01R31/319; G06; G06F; G06F2201/00; G06F2201/83
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
217 words
A method for performing a functional test of integrated circuits at speed using a tester apparatus which includes a test bus having control and data signal lines, a test bus controller for transmitting stimulus data to and receiving response data from a device under test (DUT), and a boundary-scan architecture which includes a plurality of registers coupled to the test bus including an instruction register for receiving clock and control signals from the test bus controller and storing the clock and control signals as large instruction sets, a boundary-scan register including a plurality of input and output boundary-scan cells for buffering stimulus and response signals associated with the DUT, a bypass register for providing a signal path by which test data can be routed without interference with a subsequent serially connected DUT, and a test data register for storing test parameters associated with the DUT, said method comprising the steps of: a) generating a high frequency clock signal as stimuli is applied to the DUT; b) dividing said high frequency clock signal into a desired test rate frequency in response to test rate information received from the test data register; and c) determining a number of test cycles for the DUT from divided clock signal information and test cycle count data received from the test data register.
Claim 2
Independent Claim
217 words
A method for performing a functional test of integrated circuits at speed using a tester apparatus which includes a test bus having control and data signal lines, a test bus controller for transmitting stimulus data to and receiving response data from a device under test (DUT), and a boundary-scan architecture which includes a plurality of registers coupled to the test bus including an instruction register for receiving clock and control signals from the test bus controller and storing the clock and control signals as large instruction sets, a boundary-scan register including a plurality of input and output boundary-scan cells for buffering stimulus and response signals associated with the DUT, a bypass register for providing a signal path by which test data can be routed without interference with a subsequent serially connected DUT, and a test data register for storing test parameters associated with the DUT, said method comprising the steps of: a) generating a high frequency clock signal as stimuli is applied to the DUT; b) dividing said high frequency clock signal into a desired test rate frequency in response to test rate information received from the test data register; and c) determining a number of test cycles for the DUT from divided clock signal information and test cycle count data received from the test data register.
Claim 3
Dependent Claim
74 words
A method for performing a functional test of integrated circuits at speed as in claim 1 further comprising the steps of: a) selectively delaying stimulus and response data transmitted to and received from the DUT; and b) compressing at speed response data collected at each output boundary-scan cell of the boundary-scan register into a signature for comparison with a known good signature for said DUT to verify that said DUT is a good device.
Claim 4
Dependent Claim
52 words
A method for performing a functional test of integrated circuits at speed as in claim 2 wherein each of the output boundary-scan cells of the boundary-scan register includes logic means for performing at speed test of the DUT from functional, algorithmic and random test pattern data received from the test data register.
Claim 5
Dependent Claim
41 words
A method for performing a functional test of integrated circuits at speed as in claim 3 wherein all steps for at speed testing are in the form of private instructions which supplement the public instructions of the IEEE 1149.1 test standard.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-06 | 1998-09-05 | 1999-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-06 | 2002-09-05 | 2003-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-06 | 2006-09-05 | 2007-03-07 | $7700.00 | Window Closed / Lapsed |