Patent US5994915A successfully refreshed from Google Patents.
US5994915A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Reduced terminal testing system
Assignee: Micron Technology Inc
•
Filing: 1997-12-19
•
Granted: 1999-11-30
•
Expires: 2017-12-19
Abstract
Abstract A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signals unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die. A wafer mode controlling system includes a system controller to control application of the alternating signals and other signals to the dice on the wafer. The semiconductor wafer mode controlling system may also control a probe positioning controller including an array of probes that selectively brings the probes into contact with the probe pads, whereby the alternating signal having the certain characteristics is transmitted from the probe to the circuitry through the probe pad and conductive path and the circuitry of each of the dice is placed into the mode.
Inventors
- 👤 Warren M. Farnworth
- 👤 Leland R. Nevill
- 👤 Raymond J. Beffa
- 👤 Eugene H. Cloud
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:28
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/286; G01R31/2868; G01R31/2832; G01R31/2836; G01R31/2839; G01R31/2841; G01R31/2856; G01R31/317; G01R31/31701; G01R31/3181; G01R31/3185; G01R31/318505; G01R31/318511; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/1201; G11C29/48; H; H10; H10P; H10P74/00; H10P74/27; H10P74/273; G01R31/282; G01R31/2831
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
342 words
A semiconductor wafer mode controlling system for the testing of modes of the circuitry of a plurality of semiconductor dice located on said semiconductor wafer, the system comprising: a system controller including a signal generation device generating an alternating signal having a predetermined characteristic; a wafer including a substrate, a plurality of probe pads, a plurality of semiconductor dice, each semiconductor die of said plurality of semiconductor dice have at least one circuit and at least one bond pad located thereon, said plurality of semiconductor dice located on the substrate, and a plurality of conductive paths extending between the plurality of probe pads and the at least one bond pad located on a semiconductor die of said plurality of semiconductor dice, at least one conductive path extending between at least one bond pad on at least one semiconductor die of said plurality of semiconductor dice and at least one probe pad of said plurality of probe pads, each semiconductor die of the plurality of semiconductor dice includes at least one circuit placed into a mode after receipt of the alternating signal having a predetermined characteristic by the at least one circuit, a conductive path of the plurality of conductive paths carrying a V CC power signal substantially simultaneously with the alternating signal; and a probe positioning controller including an array of probes, at least one probe of the array of probes selectively contacting at least one probe pad of the plurality of probe pads, the alternating signal having a predetermined characteristic of the signal generation device transmitted from the at least one probe of the array of probes to the at least one circuit of the at least one semiconductor die of said plurality of semiconductor die by contacting a probe pad of the plurality of probe pads having at least one conductive path of the plurality of conductive paths connected thereto and to at least one bond pad of the semiconductor device placing the at least one circuit of the semiconductor die of said plurality of semiconductor dice into the mode.
Claim 2
Dependent Claim
342 words
A semiconductor wafer mode controlling system for the testing of modes of the circuitry of a plurality of semiconductor dice located on said semiconductor wafer, the system comprising: a system controller including a signal generation device generating an alternating signal having a predetermined characteristic; a wafer including a substrate, a plurality of probe pads, a plurality of semiconductor dice, each semiconductor die of said plurality of semiconductor dice have at least one circuit and at least one bond pad located thereon, said plurality of semiconductor dice located on the substrate, and a plurality of conductive paths extending between the plurality of probe pads and the at least one bond pad located on a semiconductor die of said plurality of semiconductor dice, at least one conductive path extending between at least one bond pad on at least one semiconductor die of said plurality of semiconductor dice and at least one probe pad of said plurality of probe pads, each semiconductor die of the plurality of semiconductor dice includes at least one circuit placed into a mode after receipt of the alternating signal having a predetermined characteristic by the at least one circuit, a conductive path of the plurality of conductive paths carrying a V CC power signal substantially simultaneously with the alternating signal; and a probe positioning controller including an array of probes, at least one probe of the array of probes selectively contacting at least one probe pad of the plurality of probe pads, the alternating signal having a predetermined characteristic of the signal generation device transmitted from the at least one probe of the array of probes to the at least one circuit of the at least one semiconductor die of said plurality of semiconductor die by contacting a probe pad of the plurality of probe pads having at least one conductive path of the plurality of conductive paths connected thereto and to at least one bond pad of the semiconductor device placing the at least one circuit of the semiconductor die of said plurality of semiconductor dice into the mode.
Claim 3
Dependent Claim
49 words
The system of claim 1, wherein the signal generation device generates more than one type of alternating signal and the circuit of each die of the plurality of dice are placed into different modes depending on the type of signal that is received by the circuit of the die.
Claim 4
Dependent Claim
20 words
The system of claim 1, wherein the circuit of a die of the plurality of dice includes a local oscillator.
Claim 5
Dependent Claim
22 words
The system of claim 1, further comprising: at least one component located on a conductive path of the plurality of conductive paths.
Claim 6
Dependent Claim
37 words
The system of claim 1, further comprising: at least one die of the plurality of dice including at least one contact separating the circuit of the die from a conductive path of the plurality of conductive paths.
Claim 7
Dependent Claim
16 words
The system of claim 1, wherein the system controller analyzes signals from the plurality of dice.
Claim 8
Dependent Claim
23 words
The system of claim 1, wherein at least one die of the plurality of dice includes other contacts not receiving the alternating signals.
Claim 9
Dependent Claim
26 words
The system of claim 1, wherein each die of the plurality of dice is connected to only one conductive path of the plurality of conductive paths.
References Cited (Backward Citations)
US3963985A
Cited
US4038599A
Cited
US4434401A
Cited
US5198752A
Cited
US5034688A
Cited
US5034685A
Cited
US4899107A
Cited
US4968931A
Cited
US5010296A
Cited
US5123850A
Cited
US5070297A
Cited
US5198753A
Cited
US5325052A
Cited
US5339273A
Cited
US5327074A
Cited
US5436559A
Cited
US5266894A
Cited
US5342807A
Cited
US5302891A
Cited
US5410261A
Cited
US5457401A
Cited
US5210485A
Cited
US5457400A
Cited
US5483175A
Cited
US5389556A
Cited
US5442282A
Cited
US5286656A
Cited
US5548884A
Cited
US5504369A
Cited
US5446695A
Cited
US5859442A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-29 | 2003-05-31 | 2003-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-29 | 2007-05-31 | 2007-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-29 | 2011-05-31 | 2011-11-30 | $7700.00 | Window Closed / Lapsed |