US4038599A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High density wafer contacting and test system
Assignee: International Business Machines Corp
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Filing: 1974-12-30
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Granted: 1977-07-26
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Expires: 1994-12-30
Abstract
Abstract A contactor structure employed in a high speed electronic test system for testing the electrical integrity of the conductive paths (or lines) in the packaging substrate prior to the mounting and connection thereto of the high circuit density monolithic devices. The contactor structure includes a semiconductor space transformer fabricated by large scale integration techniques and containing a plurality of discrete first integrated circuits. The first integrated circuits of the space transformer being respectively electrically connected to said electrical probes. Second integrated circuitry interconnecting said first integrated circuits is also contained within said semiconductor space transformer. Under control of said test system said second integrated circuitry selectively energizes, selected first and second ones of said first integrated circuits. Each of said first integrated circuits contains circuitry, whereby said selected first and second ones of said first circuits will manifest the electrical integrity of the electrical path there between.
Inventors
- 👤 Ronald Bove
- 👤 Eric M. Hubacher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:05
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2853; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/07314; G01R31/2886
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
166 words
A space transformer for use in an electronic test system for testing micro-miniature electronic devices, said space transformer comprising: a monolithic silicon structure; said silicon structure containing, a first binary decoder circuit adapted to receive a first set of m binary inputs and provide a first set of 2 m binary outputs, a second binary decoder circuit adapted to receive a second set of m binary inputs and provide a second set of 2 m binary outputs, a third binary decoder circuit adapted to receive a third set of m binary inputs and provide a third set of 2 m binary outputs, a fourth binary decoder circuit adapted to receive a fourth set of m binary inputs and provide a fourth set of 2 m binary outputs, where m may be any integer number, a plurality of logic circuits selectively connected to said outputs of said first, second, third and fourth binary decoders, an array of exposed conductive pads connected to said plurality of logic circuits.
Claim 2
Dependent Claim
166 words
A space transformer for use in an electronic test system for testing micro-miniature electronic devices, said space transformer comprising: a monolithic silicon structure; said silicon structure containing, a first binary decoder circuit adapted to receive a first set of m binary inputs and provide a first set of 2 m binary outputs, a second binary decoder circuit adapted to receive a second set of m binary inputs and provide a second set of 2 m binary outputs, a third binary decoder circuit adapted to receive a third set of m binary inputs and provide a third set of 2 m binary outputs, a fourth binary decoder circuit adapted to receive a fourth set of m binary inputs and provide a fourth set of 2 m binary outputs, where m may be any integer number, a plurality of logic circuits selectively connected to said outputs of said first, second, third and fourth binary decoders, an array of exposed conductive pads connected to said plurality of logic circuits.
Claim 3
Dependent Claim
37 words
A space transformer for use in an electronic test system for testing micro-miniature electronic devices as recited in claim 1 further characterized in that said plurality of logic circuits is equal in number to m 2 .
Claim 4
Dependent Claim
99 words
A space transformer for use in an electronic test system for testing micro-miniature electronic devices as recited in claim 2 further characterized in that each of said m 2 logic circuits is connected to a discrete output of each of said first, second third and fourth binary decoders, whereby each of said m 2 logic circuits is uniquely connected to said first, second, third and fourth binary decoders, whereby said first, second, third and fourth sets of m binary inputs may be employed to select and condition a predetermined first and second ones of said m 2 logic circuits.
Claim 5
Dependent Claim
77 words
A space transformer for use in an electronic test system for testing micro-miniature electronic devices as recited in claim 3 wherein each of said m 2 logic circuits is essentially identical to each other one of said m 2 logic circuits and said predetermined first one of said m 2 logic circuits is adapted to perform a first function and said predetermined second one of said m 2 logic circuits is adapted to perform a second function.
Claim 6
Dependent Claim
76 words
In an electronic test system for electrically testing very small electronic structures, a contactor structure for making electrical contact with an electrical structure undergoing test, said contactor comprising: a space transformer as recited in claim 4; a probe assembly electrically and mechanically mated with said contactor structure, said probe assembly having a plurality of probes each of said probes being in electrical contact with one of said array of exposed conductive pads of said space transformer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-25 | 1981-01-24 | 1981-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-25 | 1985-01-24 | 1985-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-25 | 1989-01-24 | 1989-07-26 | $7700.00 | Window Closed / Lapsed |