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US5989958A
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Flash memory with microcrystalline silicon carbide film floating gate
Assignee: Micron Technology Inc
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Filing: 1998-08-20
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Granted: 1999-11-23
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Expires: 2018-08-20
Abstract
Abstract A memory is described which has memory cells that store data using hot electron injection. The data is erased through electron tunneling. The memory cells are described as floating gate transistors wherein the floating gate is fabricated using a conductive layer of microcrystalline silicon carbide particles. The microcrystalline silicon carbide particles are in contact such that a charge stored on the floating gate is shared between the particles. The floating gate has a reduced electron affinity to allow for data erase operations using lower voltages.
Inventors
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:54
CPC Classifications
B; B82; B82Y; B82Y10/00; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D30/6891; H10D30/6893; H10D64/00; H10D64/60; H10D64/66; H10D64/667; Y; Y10; Y10S; Y10S438/00; Y10S438/931
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
84 words
A method of fabricating a memory cell, the method comprising: fabricating a source and drain in a semiconductor substrate, the source and drain being separated to define a channel region between the source and drain; fabricating a first insulating layer over the channel region; fabricating a floating gate over the first insulating layer, the floating gate comprising a conductive film of microcrystalline silicon carbide particles; fabricating a second insulating layer over the floating gate; and fabricating a control gate over the second insulating layer.
Claim 2
Independent Claim
84 words
A method of fabricating a memory cell, the method comprising: fabricating a source and drain in a semiconductor substrate, the source and drain being separated to define a channel region between the source and drain; fabricating a first insulating layer over the channel region; fabricating a floating gate over the first insulating layer, the floating gate comprising a conductive film of microcrystalline silicon carbide particles; fabricating a second insulating layer over the floating gate; and fabricating a control gate over the second insulating layer.
Claim 3
Dependent Claim
23 words
The method of claim 1, wherein fabricating a first insulating layer comprises fabricating a layer of oxide having thickness of about 100 Angstroms.
Claim 4
Dependent Claim
43 words
The method of claim 1, wherein fabricating a floating gate comprises a floating gate comprising a conductive film of microcrystalline silicon carbide particles wherein the microcrystalline silicon carbide particles each have a general diameter in the range of about 30 to 100 Angstroms.
Claim 5
Independent Claim
80 words
A method of producing a memory cell, comprising: forming a source and a drain in a semiconductor substrate, wherein the source and the drain are separated by a channel region; forming a first insulating layer over the channel region; forming a floating gate over the first insulating layer, wherein the floating gate comprises a conductive film of microcrystalline silicon carbide particles; forming a second insulating layer over the floating gate; and forming a control gate over the second insulating layer.
Claim 6
Independent Claim
80 words
A method of producing a memory cell, comprising: forming a source and a drain in a semiconductor substrate, wherein the source and the drain are separated by a channel region; forming a first insulating layer over the channel region; forming a floating gate over the first insulating layer, wherein the floating gate comprises a conductive film of microcrystalline silicon carbide particles; forming a second insulating layer over the floating gate; and forming a control gate over the second insulating layer.
Claim 7
Dependent Claim
43 words
The method of claim 4 wherein forming a floating gate comprises a floating gate comprising a conductive film of microcrystalline silicon carbide particles wherein the microcrystalline silicon carbide particles each have a general diameter in the range of about 30 to 100 Angstroms.
Claim 8
Independent Claim
80 words
A method of producing a memory cell, comprising: forming a source and a drain in a semiconductor substrate, wherein the source and the drain are separated by a channel region; forming a first insulating layer over the channel region; forming a floating gate over the first insulating layer, wherein the floating gate comprises a conductively-doped film of microcrystalline silicon carbide particles; forming a second insulating layer over the floating gate; and forming a control gate over the second insulating layer.
Claim 9
Independent Claim
80 words
A method of producing a memory cell, comprising: forming a source and a drain in a semiconductor substrate, wherein the source and the drain are separated by a channel region; forming a first insulating layer over the channel region; forming a floating gate over the first insulating layer, wherein the floating gate comprises a conductively-doped film of microcrystalline silicon carbide particles; forming a second insulating layer over the floating gate; and forming a control gate over the second insulating layer.
Claim 10
Independent Claim
75 words
A method of producing a memory cell, comprising: forming a source and a drain in a semiconductor substrate, wherein the source and the drain are separated by a channel region; forming a first insulating layer over the channel region; depositing a film of microcrystalline silicon carbide particles over the first insulating layer; forming a second insulating layer over the film of microcrystalline silicon carbide particles; and forming a control gate over the second insulating layer.
Claim 11
Independent Claim
75 words
A method of producing a memory cell, comprising: forming a source and a drain in a semiconductor substrate, wherein the source and the drain are separated by a channel region; forming a first insulating layer over the channel region; depositing a film of microcrystalline silicon carbide particles over the first insulating layer; forming a second insulating layer over the film of microcrystalline silicon carbide particles; and forming a control gate over the second insulating layer.
Claim 12
Dependent Claim
30 words
The method of claim 7, wherein depositing a film comprises a method selected from the group consisting of plasma enhanced chemical vapor deposition and other enhanced chemical vapor deposition techniques.
Claim 13
Independent Claim
98 words
A method of producing a memory cell, comprising: forming a source and a drain in a semiconductor substrate, wherein the source and the drain are separated by a channel region; forming a first insulating layer over the channel region; depositing a film of microcrystalline silicon carbide particles over the first insulating layer; doping the film of microcrystalline silicon carbide particles to have a conductivity, thereby producing a conductively-doped film of microcrystalline silicon carbide particles; forming a second insulating layer over the conductively-doped film of microcrystalline silicon carbide particles; and forming a control gate over the second insulating layer.
Claim 14
Independent Claim
98 words
A method of producing a memory cell, comprising: forming a source and a drain in a semiconductor substrate, wherein the source and the drain are separated by a channel region; forming a first insulating layer over the channel region; depositing a film of microcrystalline silicon carbide particles over the first insulating layer; doping the film of microcrystalline silicon carbide particles to have a conductivity, thereby producing a conductively-doped film of microcrystalline silicon carbide particles; forming a second insulating layer over the conductively-doped film of microcrystalline silicon carbide particles; and forming a control gate over the second insulating layer.
Claim 15
Dependent Claim
30 words
The method of claim 9, wherein depositing a film comprises a method selected from the group consisting of plasma enhanced chemical vapor deposition and other enhanced chemical vapor deposition techniques.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-22 | 2003-05-24 | 2003-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-22 | 2007-05-24 | 2007-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-22 | 2011-05-24 | 2011-11-23 | $7700.00 | Window Closed / Lapsed |