US5980092A
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Method and apparatus for optimizing a gated clock structure using a standard optimization tool
Assignee: Unisys Corp
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Filing: 1996-11-19
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Granted: 1999-11-09
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Expires: 2016-11-19
Abstract
Abstract A method and apparatus for using an optimization tool to optimize a design that uses a gated clock structure. In short, the present invention allows a standard optimizer tool to determine the relative timing of two or more signals that arrive at a logic gate, wherein the logic gate forms a gated clock signal. Typically, standard optimizer tools can only check the relative timing between two or more signals that arrive at a storage element. In accordance with the present invention, selected logic gates may be modeled as a storage element. Thus, a standard optimizer tool may be used to correctly optimize a design that uses a gated clock structure, and in particular, to correctly optimize the logic that provides the clock and enable signals to a clock gating element.
Inventors
- 👤 Kenneth E. Merryman
- 👤 Kevin C. Cleereman
- 👤 Kenneth L. Engelbrecht
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:57
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/3312; G06F2117/00; G06F2117/04; G06F2119/00; G06F2119/12
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
96 words
A method for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of: a. modeling the logic element as a storage element, wherein the storage element has a predefined setup time associated therewith; and b. optimizing the circuit design using an optimization tool, wherein the optimization tool optimizes the circuit design such that the first signal arrives at the storage element relative to the second signal within the predefined setup time.
Claim 2
Independent Claim
96 words
A method for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of: a. modeling the logic element as a storage element, wherein the storage element has a predefined setup time associated therewith; and b. optimizing the circuit design using an optimization tool, wherein the optimization tool optimizes the circuit design such that the first signal arrives at the storage element relative to the second signal within the predefined setup time.
Claim 3
Independent Claim
96 words
A method for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of: a. modeling the logic element as a storage element, wherein the storage element has a predefined hold time associated therewith; and b. optimizing the circuit design using an optimization tool, wherein the optimization tool optimizes the circuit design such that the first signal arrives at the storage element relative to the second signal within the predefined hold time.
Claim 4
Independent Claim
96 words
A method for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of: a. modeling the logic element as a storage element, wherein the storage element has a predefined hold time associated therewith; and b. optimizing the circuit design using an optimization tool, wherein the optimization tool optimizes the circuit design such that the first signal arrives at the storage element relative to the second signal within the predefined hold time.
Claim 5
Independent Claim
100 words
A method for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of: a. modeling the logic element as a storage element, wherein the storage element has a predefined setup and hold time associated therewith; and b. optimizing the circuit design using an optimization tool, wherein the optimization tool optimizes the circuit design such that the first signal arrives at the storage element relative to the second signal within the predefined setup and hold times.
Claim 6
Independent Claim
100 words
A method for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of: a. modeling the logic element as a storage element, wherein the storage element has a predefined setup and hold time associated therewith; and b. optimizing the circuit design using an optimization tool, wherein the optimization tool optimizes the circuit design such that the first signal arrives at the storage element relative to the second signal within the predefined setup and hold times.
Claim 7
Independent Claim
97 words
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the method comprising the steps of: a. modeling the logic element as a storage element, wherein the storage element has a predefined setup time associated therewith; and b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the clock control signal arrives at the storage element within the predefined setup time of the clock signal.
Claim 8
Independent Claim
97 words
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the method comprising the steps of: a. modeling the logic element as a storage element, wherein the storage element has a predefined setup time associated therewith; and b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the clock control signal arrives at the storage element within the predefined setup time of the clock signal.
Claim 9
Independent Claim
97 words
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the method comprising the steps of: a. modeling the logic element as a storage element, wherein the storage element has a predefined hold time associated therewith; and b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the clock control signal arrives at the storage element within the predefined hold time of the clock signal.
Claim 10
Independent Claim
97 words
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the method comprising the steps of: a. modeling the logic element as a storage element, wherein the storage element has a predefined hold time associated therewith; and b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the clock control signal arrives at the storage element within the predefined hold time of the clock signal.
Claim 11
Independent Claim
101 words
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the method comprising the steps of: a. modeling the logic element as a storage element, wherein the storage element has a predefined setup and hold time associated therewith; and b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the clock control signal arrives at the storage element within the predefined setup and hold times of the clock signal.
Claim 12
Independent Claim
101 words
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the method comprising the steps of: a. modeling the logic element as a storage element, wherein the storage element has a predefined setup and hold time associated therewith; and b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the clock control signal arrives at the storage element within the predefined setup and hold times of the clock signal.
Claim 13
Dependent Claim
13 words
A method according to claim 6 wherein the storage element is a register.
Claim 14
Dependent Claim
38 words
A method according to claim 7 wherein said register has a data input and a clock input, and the clock signal is provided to the clock input and the clock control signal is provided to the data input.
Claim 15
Independent Claim
85 words
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the method comprising the steps of: a. replacing the logic element with a storage element; and b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the clock control signal arrives at the storage element within a predetermined time of the clock signal.
Claim 16
Independent Claim
85 words
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the method comprising the steps of: a. replacing the logic element with a storage element; and b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the clock control signal arrives at the storage element within a predetermined time of the clock signal.
Claim 17
Dependent Claim
25 words
A method according to claim 9 further comprising the step of: c. replacing the storage element with the logic element after the optimization step (b).
Claim 18
Dependent Claim
18 words
A method according to claim 10 wherein said optimization step (b) does not optimize the storage element itself.
Claim 19
Independent Claim
151 words
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the clock signal providing a clock pulse wherein the clock pulse has a leading edge, a trailing edge, and a clock pulse width, the clock control signal providing a control pulse wherein the control pulse may overlap the leading edge of the clock pulse by a desired leading overlap amount and may overlap the trailing edge of the clock pulse by a desired trailing overlap amount, the method comprising the steps of: a. modeling the logic element as a storage element; and b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the control pulse overlaps the leading edge of the clock pulse by the desired leading overlap amount.
Claim 20
Independent Claim
151 words
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the clock signal providing a clock pulse wherein the clock pulse has a leading edge, a trailing edge, and a clock pulse width, the clock control signal providing a control pulse wherein the control pulse may overlap the leading edge of the clock pulse by a desired leading overlap amount and may overlap the trailing edge of the clock pulse by a desired trailing overlap amount, the method comprising the steps of: a. modeling the logic element as a storage element; and b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the control pulse overlaps the leading edge of the clock pulse by the desired leading overlap amount.
Claim 21
Independent Claim
151 words
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the clock signal providing a clock pulse wherein the clock pulse has a leading edge, a trailing edge, and a clock pulse width, the clock control signal providing a control pulse wherein the control pulse may overlap the leading edge of the clock pulse by a desired leading overlap amount and may overlap the trailing edge of the clock pulse by a desired trailing overlap amount, the method comprising the steps of: a. modeling the logic element as a storage element; and b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the control pulse overlaps the trailing edge of the clock pulse by the desired trailing overlap amount.
Claim 22
Independent Claim
151 words
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the clock signal providing a clock pulse wherein the clock pulse has a leading edge, a trailing edge, and a clock pulse width, the clock control signal providing a control pulse wherein the control pulse may overlap the leading edge of the clock pulse by a desired leading overlap amount and may overlap the trailing edge of the clock pulse by a desired trailing overlap amount, the method comprising the steps of: a. modeling the logic element as a storage element; and b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the control pulse overlaps the trailing edge of the clock pulse by the desired trailing overlap amount.
Claim 23
Independent Claim
166 words
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the clock signal providing a clock pulse wherein the clock pulse has a leading edge, a trailing edge, and a clock pulse width, the clock control signal providing a control pulse wherein the control pulse may overlap the leading edge of the clock pulse by a desired leading overlap amount and may overlap the trailing edge of the clock pulse by a desired trailing overlap amount, the method comprising the steps of: a. modeling the logic element as a storage element; and b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the control pulse overlaps the leading edge of the clock pulse by the desired leading overlap amount and overlaps the trailing edge of the clock pulse by the desired trailing overlap amount.
Claim 24
Independent Claim
166 words
A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the clock signal providing a clock pulse wherein the clock pulse has a leading edge, a trailing edge, and a clock pulse width, the clock control signal providing a control pulse wherein the control pulse may overlap the leading edge of the clock pulse by a desired leading overlap amount and may overlap the trailing edge of the clock pulse by a desired trailing overlap amount, the method comprising the steps of: a. modeling the logic element as a storage element; and b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the control pulse overlaps the leading edge of the clock pulse by the desired leading overlap amount and overlaps the trailing edge of the clock pulse by the desired trailing overlap amount.
Claim 25
Dependent Claim
88 words
Apparatus for,optimizing a circuit design having a logic element therein such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, comprising: a. modeling means for modeling the logic element as a storage element, wherein the storage element has a predetermined setup time associated therewith; and b. optimizing means coupled to said modeling means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined setup time of the second signal.
Claim 26
Dependent Claim
88 words
Apparatus for,optimizing a circuit design having a logic element therein such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, comprising: a. modeling means for modeling the logic element as a storage element, wherein the storage element has a predetermined setup time associated therewith; and b. optimizing means coupled to said modeling means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined setup time of the second signal.
Claim 27
Dependent Claim
89 words
Apparatus for optimizing a circuit design having a logic element therein such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, comprising: a. modeling means for modeling the logic element as a storage element, wherein the storage element has a predetermined hold time associated therewith; and b. optimizing means coupled to said modeling means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined hold time of the second signal.
Claim 28
Dependent Claim
89 words
Apparatus for optimizing a circuit design having a logic element therein such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, comprising: a. modeling means for modeling the logic element as a storage element, wherein the storage element has a predetermined hold time associated therewith; and b. optimizing means coupled to said modeling means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined hold time of the second signal.
Claim 29
Dependent Claim
92 words
Apparatus for,optimizing a circuit design having a logic element therein such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, comprising: a. modeling means for modeling the logic element as a storage element, wherein the storage element has a predetermined setup and hold time associated therewith; and b. optimizing means coupled to said modeling means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined setup and hold times of the second signal.
Claim 30
Dependent Claim
92 words
Apparatus for,optimizing a circuit design having a logic element therein such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, comprising: a. modeling means for modeling the logic element as a storage element, wherein the storage element has a predetermined setup and hold time associated therewith; and b. optimizing means coupled to said modeling means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined setup and hold times of the second signal.
Claim 31
Dependent Claim
13 words
Apparatus according to claim 17 wherein said logic element comprises a two-input gate.
Claim 32
Dependent Claim
57 words
Apparatus according to claim 18 wherein said modeling means comprises a timing model of a register bit having a clock and a data input, the clock input being coupled to a first one of the inputs of the two-input gate and the data input being coupled to the second one of the inputs of the two-input gate.
Claim 33
Dependent Claim
21 words
Apparatus according to claim 19 wherein said timing model defines the setup time and the hold time for the register bit.
Claim 34
Dependent Claim
13 words
Apparatus according to claim 20 wherein said optimizing means comprises an optimization tool.
Claim 35
Dependent Claim
37 words
Apparatus according to claim 21 wherein said optimization tool checks the setup time and the hold time of the register bit, thereby checking when the first signal arrives at the register bit relative to the second signal.
Claim 36
Dependent Claim
93 words
Apparatus for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of: a. substituting means for substituting the logic element with a storage element wherein the storage element has a predetermined setup time associated therewith; and b. optimizing means coupled to said substituting means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined setup time of the second signal.
Claim 37
Dependent Claim
93 words
Apparatus for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of: a. substituting means for substituting the logic element with a storage element wherein the storage element has a predetermined setup time associated therewith; and b. optimizing means coupled to said substituting means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined setup time of the second signal.
Claim 38
Dependent Claim
93 words
Apparatus for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of: a. substituting means for substituting the logic element with a storage element wherein the storage element has a predetermined hold time associated therewith; and b. optimizing means coupled to said substituting means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined hold time of the second signal.
Claim 39
Dependent Claim
93 words
Apparatus for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of: a. substituting means for substituting the logic element with a storage element wherein the storage element has a predetermined hold time associated therewith; and b. optimizing means coupled to said substituting means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined hold time of the second signal.
Claim 40
Dependent Claim
97 words
Apparatus for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of: a. substituting means for substituting the logic element with a storage element wherein the storage element has a predetermined setup and hold time associated therewith; and b. optimizing means coupled to said substituting means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined setup and hold times of the second signal.
Claim 41
Dependent Claim
97 words
Apparatus for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of: a. substituting means for substituting the logic element with a storage element wherein the storage element has a predetermined setup and hold time associated therewith; and b. optimizing means coupled to said substituting means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined setup and hold times of the second signal.
Claim 42
Dependent Claim
19 words
Apparatus according to claim 25 further comprising a re-substituting means for re-substituting the logic element for the storage element.
References Cited (Backward Citations)
US4758953A
Cited
US5050091A
Cited
US4831543A
Cited
US5267175A
Cited
US5175696A
Cited
US5222029A
Cited
US5640547A
Cited
US4918614A
Cited
US4924430A
Cited
US5164908A
Cited
US5095454A
Cited
US5490268A
Cited
US5359537A
Cited
US5255363A
Cited
US5406497A
Cited
US5416721A
Cited
US5357440A
Cited
US5355317A
Cited
US5359523A
Cited
US5490266A
Cited
US5418954A
Cited
US5485396A
Cited
US5341309A
Cited
US5349659A
Cited
US5398195A
Cited
US5418733A
Cited
US5361357A
Cited
US5491640A
Cited
US5448497A
Cited
US5452239A
Cited
US5483461A
Cited
US5579510A
Cited
US5440720A
Cited
US5644499A
Cited
US5572717A
Cited
US5493508A
Cited
US5774371A
Cited
US5507029A
Cited
US5740347A
Cited
US5740067A
Cited
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