Patent US5963825A successfully refreshed from Google Patents.
US5963825A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabrication of semiconductor fuse with polysilicon plate
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 1992-08-26
•
Granted: 1999-10-05
•
Expires: 2012-08-26
Abstract
Abstract A fusible link and method for its fabrication. A polysilicon pad is formed on top of an insulating layer and covered with a second insulating layer. A trench is selectively etched into the second insulating layer exposing the top of the polysilicon pad. An fusible aluminum link is then formed over the second insulating layer and trench and conformal therewith. When a programming current is driven through the link, the aluminum melts and is absorbed by the polysilicon pad, thereby preventing the link's growback.
Inventors
- 👤 Steven S. Lee
- 👤 Gayle W. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 03:10
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/493; G; G11; G11C; G11C17/00; G11C17/14; G11C17/16
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
102 words
A method for fabricating a semiconductor fuse, comprising: providing a first insulating layer; forming a polysilicon pad on top of said layer; forming a second insulating layer which covers said polysilicon pad and first insulating layer; selectively etching said second layer to provide a trench having sidewalls in said second insulating layer and a bottom formed by an upper surface of said polysilicon pad; and forming a fusible link across said second layer and trench and conformal therewith; wherein a programming current through said link melts said link, and said polysilicon pad absorbs the link when melted, thereby preventing the link's growback.
Claim 2
Independent Claim
102 words
A method for fabricating a semiconductor fuse, comprising: providing a first insulating layer; forming a polysilicon pad on top of said layer; forming a second insulating layer which covers said polysilicon pad and first insulating layer; selectively etching said second layer to provide a trench having sidewalls in said second insulating layer and a bottom formed by an upper surface of said polysilicon pad; and forming a fusible link across said second layer and trench and conformal therewith; wherein a programming current through said link melts said link, and said polysilicon pad absorbs the link when melted, thereby preventing the link's growback.
Claim 3
Dependent Claim
22 words
The method of claim 1 wherein said pad functions as an etch stop for the selective etch of said second insulating layer.
Claim 4
Dependent Claim
33 words
The method of claim 1 wherein said step of forming said fusible link includes: depositing a layer of metal over said second layer and trench; and patterning said metal to form said link.
Claim 5
Dependent Claim
46 words
The method of claim 3 wherein said link is patterned into a conductive line having a necked down region, wherein said necked down region is bounded by first and second transition regions, and wherein at least a portion of said necked down region overlies said trench.
Claim 6
Dependent Claim
31 words
The method of claim 4 wherein said link melts at a break region, said break region occurring where said necked down region meets the intersection of a sidewall and polysilicon pad.
Claim 7
Dependent Claim
19 words
The method of claim 5 wherein said first transition region but not said second transition region overlies said trench.
Claim 8
Dependent Claim
17 words
The method of claim 5 wherein neither said first nor said second transition region overlies said trench.
Claim 9
Dependent Claim
45 words
The method of claim 5 wherein said selective etching step includes: providing a second trench having sidewalls in said second insulating layer and a bottom formed by an upper surface of said polysilicon pad; wherein said first and second transition regions overlie said respective trenches.
References Cited (Backward Citations)
JPS5220781A
Cited
US4045310A
Cited
US4064493A
Cited
GB2005078A
Cited
US4198744A
Cited
US4312046A
Cited
JPS5685846A
Cited
US4692787A
Cited
JPS574139A
Cited
US4424578A
Cited
SU986198A1
Cited
JPS5860560A
Cited
JPS5864061A
Cited
US4441167A
Cited
US4476375A
Cited
US4590589A
Cited
US4903111A
Cited
US4651409A
Cited
US4751197A
Cited
US4661214A
Cited
US4647340A
Cited
EP0241046A2
Cited
US5017510A
Cited
JPS6477141A
Cited
US4947020A
Cited
JPH03124047A
Cited
US5241212A
Cited
US5120679A
Cited
US5242851A
Cited
US5258643A
Cited
WO1993004499A1
Cited
US5244836A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-04 | 2003-04-05 | 2003-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-04 | 2007-04-05 | 2007-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-04 | 2011-04-05 | 2011-10-05 | $7700.00 | Window Closed / Lapsed |