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Patent US5963801A successfully refreshed from Google Patents.
US5963801A
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Method of forming retrograde well structures and punch-through barriers using low energy implants
Assignee: Bell Semiconductor LLC
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Filing: 1996-12-19
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Granted: 1999-10-05
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Expires: 2016-12-19
Abstract
Abstract A retrograde well in a CMOS device is formed by using a low energy ion implanter. Dopant atoms are implanted into a bare surface of the device's substrate, in a direction that is orthogonal to the surface of the substrate (for a substrate having a <100> orientation). The well implant can be performed at an energy below 220 keV. Chained implants for a punch-through barrier in the retrograde well can be performed after the well implant. When the substrate is annealed, the punch-through barrier is activated at the same time as the retrograde well.
Inventors
- 👤 Sheldon Aronowitz
- 👤 Laique Khan
- 👤 James Kimball
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:53
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/21; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/314; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038; H10P30/202; H10P30/204; H10P30/222
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
136 words
A method of fabricating a CMOS device having a pair of n-channel and p-channel transistors, comprising the steps of: forming isolation islands in a substrate; doping a first region for the p-channel transistor, the first region being doped by cleaning a surface of the substrate at a location where the p-channel transistor is formed, and implanting an n-type dopant directly into the cleaned surface of the substrate at a low energy in a direction that is co-aligned with channels formed within the lattice structure of the substrate; doping a second region for the n-channel transistor by performing a blanket implant of a p-type dopant; annealing the substrate; forming gate structures over the first and second regions; forming drain and source regions in the first and second regions; and forming contacts for the source and drain regions.
Claim 2
Independent Claim
136 words
A method of fabricating a CMOS device having a pair of n-channel and p-channel transistors, comprising the steps of: forming isolation islands in a substrate; doping a first region for the p-channel transistor, the first region being doped by cleaning a surface of the substrate at a location where the p-channel transistor is formed, and implanting an n-type dopant directly into the cleaned surface of the substrate at a low energy in a direction that is co-aligned with channels formed within the lattice structure of the substrate; doping a second region for the n-channel transistor by performing a blanket implant of a p-type dopant; annealing the substrate; forming gate structures over the first and second regions; forming drain and source regions in the first and second regions; and forming contacts for the source and drain regions.
Claim 3
Dependent Claim
47 words
The method of claim 1, wherein the first region is a retrograde n-well, and wherein the method further comprises the step of performing chained implants into the n-well to create a punch-through barrier, whereby the punch-through barrier is activated along with the n-well during the annealing step.
Claim 4
Dependent Claim
19 words
The method of claim 2, wherein the chained implants are also made into the cleaned surface of the substrate.
Claim 5
Dependent Claim
64 words
The method of claim 2, further comprising the step of performing a threshold voltage adjustment after the n-well implant but before the chained implants, the threshold voltage adjustment being performed by forming an oxide layer over the substrate and implanting a p-type dopant through the oxide and into a shallow region of the substrate, wherein the chained implants are performed through the oxide layer.
Claim 6
Dependent Claim
22 words
The method of claim 2, further comprising the step of performing a threshold voltage adjustment after the chained implants have been performed.
Claim 7
Dependent Claim
35 words
The method of claim 1, wherein the substrate has an <100> orientation and wherein the n-type dopant is implanted into the first region in a direction that is orthogonal to the surface of the substrate.
Claim 8
Dependent Claim
27 words
The method of claim 1, wherein the n-type dopant is implanted in a dose between 5×10 12 phosphorus atoms/cm 2 and 1×10 14 phosphorus atoms/cm 2 .
Claim 9
Dependent Claim
19 words
The method of claim 1, wherein the implant of n-type dopant is performed at an energy below 220 keV.
Claim 10
Independent Claim
140 words
A method of fabricating a plurality of CMOS devices on a semiconductor wafer, the wafer having a <100> orientation, the method comprising the steps of: forming isolation islands in the wafer; forming an n-well mask on a surface of the wafer, the surface being exposed through the mask at locations where n-wells are formed; cleaning the exposed surface of the wafer; directing an n-type dopant towards the wafer at an energy between 150 keV and 220 keV in a direction that is orthogonal to the surface of the wafer, whereby the n-type dopant is implanted deeply below the surface of the wafer; stripping the n-well mask; performing a blanket implant of a p-type dopant; annealing the wafer; forming gate structures on the wafer; forming drain and source regions in the wafer; and forming contacts for the source and drain regions.
Claim 11
Independent Claim
140 words
A method of fabricating a plurality of CMOS devices on a semiconductor wafer, the wafer having a <100> orientation, the method comprising the steps of: forming isolation islands in the wafer; forming an n-well mask on a surface of the wafer, the surface being exposed through the mask at locations where n-wells are formed; cleaning the exposed surface of the wafer; directing an n-type dopant towards the wafer at an energy between 150 keV and 220 keV in a direction that is orthogonal to the surface of the wafer, whereby the n-type dopant is implanted deeply below the surface of the wafer; stripping the n-well mask; performing a blanket implant of a p-type dopant; annealing the wafer; forming gate structures on the wafer; forming drain and source regions in the wafer; and forming contacts for the source and drain regions.
Claim 12
Dependent Claim
34 words
The method of claim 9, further comprising the step of performing chained implants into the n-wells to create punch-through barriers, whereby the punch-through barriers are activated along with the n-wells during the annealing step.
Claim 13
Dependent Claim
19 words
The method of claim 10, wherein the chained implants are also made into the cleaned surface of the substrate.
Claim 14
Dependent Claim
64 words
The method of claim 10, further comprising the step of performing a threshold voltage adjustment after the n-well implant but before the chained implants, the threshold voltage adjustment being performed by forming an oxide layer over the n-well and implanting a p-type dopant through the oxide and into a shallow region of the substrate, wherein the chained implants are performed through the oxide layer.
Claim 15
Dependent Claim
22 words
The method of claim 10, further comprising the step of performing a threshold voltage adjustment after the chained implants have been performed.
Claim 16
Dependent Claim
27 words
The method of claim 9, wherein the n-type dopant is implanted in a dose between 5×10 2 phosphorus atoms/cm 2 and 1×10 14 phosphorus atoms/cm 2 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-10-04 | 2003-04-05 | 2003-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-04 | 2007-04-05 | 2007-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-04 | 2011-04-05 | 2011-10-05 | $7700.00 | Window Closed / Lapsed |