US5693976A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOSFET device having denuded zones for forming alignment marks
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 1996-09-26
•
Granted: 1997-12-02
•
Expires: 2016-09-26
Abstract
Abstract A process for fabricating MOSFET devices, in which a denuded zone in silicon has been created during the normal process sequence, has been developed. In order to avoid the formation of deleterious oxygen precipitates, prior to the creation of the denuded zone, low temperature processing had to be used. Low temperature insulator depositions were used for the alignment mark formation, as well as for the fill for the field oxide regions. Subsequently, high temperature well formation activation anneals, resulted in the creation of the denuded zone, and thus removed the low temperature restriction for the remaining processing steps.
Inventors
- 👤 Ying-Chen Chao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:51
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/01; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0186; H10D84/0188; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/024
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
141 words
A MOSFET device structure, with reactively ion etched, straight wall trenches in a silicon substrate, filled with a chemically vapor deposited insulator, used for device isolation, and a denuded zone, used as a region for device formation, comprising: said straight wall trenches in said silicon substrate: a chemically vapor deposited insulator in said straight wall trenches; device regions between said insulator filled, straight wall trenches; polysilicon gate structures on said silicon substrate, in center of said device regions; a region in said silicon substrate, between about 5 to 50 uM below the top surface of said silicon substrate, denuded of oxygen, with oxygen precipitates below said denuded zone; and source and drain regions in the surface of said silicon substrate, in said denuded zone, between said polysilicon gate structure and between said insulator filled, straight wall trenches in said silicon substrate.
Claim 2
Dependent Claim
141 words
A MOSFET device structure, with reactively ion etched, straight wall trenches in a silicon substrate, filled with a chemically vapor deposited insulator, used for device isolation, and a denuded zone, used as a region for device formation, comprising: said straight wall trenches in said silicon substrate: a chemically vapor deposited insulator in said straight wall trenches; device regions between said insulator filled, straight wall trenches; polysilicon gate structures on said silicon substrate, in center of said device regions; a region in said silicon substrate, between about 5 to 50 uM below the top surface of said silicon substrate, denuded of oxygen, with oxygen precipitates below said denuded zone; and source and drain regions in the surface of said silicon substrate, in said denuded zone, between said polysilicon gate structure and between said insulator filled, straight wall trenches in said silicon substrate.
Claim 3
Dependent Claim
43 words
The MOSFET device structure of claim 1, wherein said straight walled trench in silicon substrate, is created by reactive ion etching, to a depth between about 3000 to 6000 Angstroms, and is filled with said insulator layer of chemically vapor deposited silicon oxide.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-01 | 2001-06-02 | 2001-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-01 | 2005-06-02 | 2005-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-01 | 2009-06-02 | 2009-12-02 | $7700.00 | Window Closed / Lapsed |