Nonvolatile semiconductor memory with a floating gate that has a bottom surface that is smaller than the upper surface

Claim 2

A nonvolatile semiconductor memory including a memory cell array having memory cells arranged in a matrix, the memory cell array comprising: a semiconductor substrate; a tunnel oxide film formed on the semiconductor substrate; floating gates including first polysilicon films formed on the tunnel oxide film and second polysilicon films formed on both sides of the respective first polysilicon films; drain and source diffusion regions embedded in the substrate, where each of the drain and source diffusion regions underlie the second polysilicon films and an edge of the first polysilicon films for each floating gate; first insulating films formed on the floating gates; and control gates formed over the first insulating films and above the first and second polysilicon films of the floating gates, wherein the memory cell array further comprising second insulating films formed on the tunnel oxide film between the first polysilicon films, the second insulating films having a predetermined thickness which is uniformly thinner than a minimum thickness of the first polysilicon films, and wherein the second polysilicon films are formed on the second insulating films, and further wherein the second insulating films are formed above the drain and source diffusion regions, and the second polysilicon films are uniformly spaced from the drain and source diffusion regions by a combined thickness of the second insulating films and the tunnel oxide film which combined thickness is substantially greater than the thickness of the tunnel oxide film that separates the edges of the first polysilicon films and the drain and source diffusion regions.

Claim 3

A nonvolatile semiconductor memory according to claim 1, wherein the second insulating films also separate the second polysilicon films of adjacent memory cells, and the second polysilicon films prevent capacitive coupling between the separated second polysilicon films of the floating gates and the semiconductor substrate.

Claim 4

A nonvolatile semiconductor memory including a memory cell array having memory cells arranged in a matrix, the memory cell comprising: a semiconductor substrate; a tunnel oxide film formed on the semiconductor substrate; a floating gate including a first polysilicon film formed on the tunnel oxide film and a second polysilicon film formed on both sides of the first polysilicon film; drain or source diffusion regions embedded in the substrate, where one of the drain or source diffusion regions underlie at least a portion of the second polysilicon film extending beyond the first polysilicon film for each floating gate; a first insulating film formed on the floating gate; and a control gate formed over the first insulating film and above the first and second polysilicon films of the floating gate, wherein the memory cell further includes a second insulating film formed on the tunnel oxide film and adjacent the first polysilicon film, the second insulating film and second polysilicon film have a combined thickness which is substantially the same as the thickness of the first polysilicon films, whereby a planarized upper surface of the floating gate facing the control gate includes surfaces of the first polysilicon film and surfaces of the second polysilicon film, and wherein the second polysilicon film covers the first polysilicon film and portions of the second insulating film, whereby the second polysilicon film is uniformly separated from the drain and source regions of the substrate by the tunnel oxide film and the second insulating film, and the first polysilicon film is separated from the substrate by only the tunnel oxide film.

Claim 5

A nonvolatile semiconductor memory including a memory cell array having memory cells arranged in a matrix, the memory cell comprising: a semiconductor substrate; a tunnel oxide film formed on the semiconductor substrate; a floating gate including a first polysilicon film formed on the tunnel oxide film and a second polysilicon film formed on both sides of the first polysilicon film; drain or source diffusion regions embedded in the substrate, where one of the drain or source diffusion regions underlie at least a portion of the second polysilicon film extending beyond the first polysilicon film for each floating gate; a first insulating film formed on the floating gate; and a control gate formed over the first insulating film and above the first and second polysilicon films of the floating gate, wherein the memory cell further includes a second insulating film formed on the tunnel oxide film and adjacent the first polysilicon film, the second insulating film and second polysilicon film have a combined thickness which is substantially the same as the thickness of the first polysilicon films, whereby a planarized upper surface of the floating gate facing the control gate includes surfaces of the first polysilicon film and surfaces of the second polysilicon film, and wherein the second polysilicon film covers the first polysilicon film and portions of the second insulating film, whereby the second polysilicon film is uniformly separated from the drain and source regions of the substrate by the tunnel oxide film and the second insulating film, and the first polysilicon film is separated from the substrate by only the tunnel oxide film.

Claim 6

A nonvolatile semiconductor memory according to claim 3, wherein the second insulating film separates a second polysilicon film of an adjacent memory cell, and the second insulating film prevents capacitive coupling between the corresponding second polysilicon film of the floating gate and the substrate.

Claim 7

A nonvolatile semiconductor memory including a memory cell array having memory cells arranged in a matrix, the memory cell comprising: a semiconductor substrate; a lower insulating film on the semiconductor substrate; a floating gate formed on the lower insulating film and over the semiconductor substrate to form a first capacitance between the floating gate and the semiconductor substrate, and the floating gate has a center polysilicon film on the lower insulating film and a side polysilicon film that abuts both sides of the center polysilicon film; an upper insulating film on both the center and side polysilicon films of the floating gate; a control gate formed over the floating gate with the upper insulating film interposed therebetween, the control gate forming a second capacitance with the floating gate; wherein the second capacitance is larger than the first capacitance.

Claim 8

A nonvolatile semiconductor memory including a memory cell array having memory cells arranged in a matrix, the memory cell comprising: a semiconductor substrate; a lower insulating film on the semiconductor substrate; a floating gate formed on the lower insulating film and over the semiconductor substrate to form a first capacitance between the floating gate and the semiconductor substrate, and the floating gate has a center polysilicon film on the lower insulating film and a side polysilicon film that abuts both sides of the center polysilicon film; an upper insulating film on both the center and side polysilicon films of the floating gate; a control gate formed over the floating gate with the upper insulating film interposed therebetween, the control gate forming a second capacitance with the floating gate; wherein the second capacitance is larger than the first capacitance.

Claim 9

A nonvolatile semiconductor memory according to claim 5, wherein the floating gate has a bottom surface which is a bottom surface of the center polysilicon film and which contributes to forming the first capacitance with the semiconductor substrate, and an upper surface which is a combined area of upper surfaces of the center and side polysilicon films which contribute to forming the second capacitance with the control gate, wherein an area of the upper surface is larger than an area of the lower surface.

Claim 10

A nonvolatile semiconductor memory according to claim 6, further comprising a source region and a drain region formed in a surface region of the semiconductor substrate, wherein the bottom surface of the center polysilicon film covers at least a part of the source region and at least a part of the drain region.

Claim 11

A nonvolatile semiconductor memory according to claim 5, wherein the floating gate in a cross section along a channel direction of the memory cell has a width of the upper surface along the channel direction that is larger than a width of the bottom surface along the channel direction.

Claim 12

A nonvolatile semiconductor memory according to claim 8, wherein the cross section of the floating gate has a "T" shape, the first portion includes a "leg" portion of the "T" shape which is formed by the center polysilicon film, and the second portion includes a "wing" portion of the "T" which is formed by the side polysilicon film and the center polysilicon film.

Claim 13

A nonvolatile semiconductor memory according to claim 5, wherein the lower insulating film is a tunnel oxide film.