Field effect transistor with a shaped gate electrode

Claim 2

A field effect transistor comprising: a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type; impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, said impurity layers constituting source.drain regions, and a region between said impurity layers defining a first channel region at said main surface; and a shaped conductive layer formed by etching on said first channel region with an insulating film interposed therebetween at said main surface, said shaped conductive layer having an upper portion and a lower portion, the upper portion being longer than the lower portion, the length of the lower portion adjacent the insulating film being substantially equal to or shorter than the length of said first channel region, and the upper and lower portions being formed of polysilicon, the upper portion polysilicon of said shaped conductive layer having a first ion impurity therein and the lower portion polysilicon of said shaped conductive layer having a second ion impurity therein, the first and second ion impurities being different elements and being selected so that the lower portion has a faster etch rate as compared with an etch rate of the upper portion to thereby determine the lengths of the lower portion and upper portion under the same etching conditions.

Claim 3

A field effect transistor comprising: a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type; impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, said impurity layer constituting source.drain regions, and a region between said impurity layers defining a first channel region at said main surface, each of said impurity layers comprising a first impurity layer portion having a first impurity concentration and a second impurity layer portion having a second impurity concentration which is higher than the first impurity concentration, and said first channel region being defined by a first distance between said first impurity layer portions and a second channel region being defined by a second distance between said second impurity layer portions; and a shaped conductive layer formed by etching on said first channel region with an insulating film interposed therebetween at said main surface, said shaped conductive layer having an upper portion and a lower portion, the upper portion begin longer than the lower portion, the length of the lower portion adjacent the insulating film being substantially equal to or shorter than the length of said first channel region, and the upper and lower portions being formed of polysilicon, the upper portion polysilicon of said shaped conductive layer having a first ion impurity therein and the lower portion polysilicon of said shaped conductive layer having a second ion impurity therein, the first and second ion impurities being different elements and being selected so that the lower portion has a faster etch rate as compared with an etch rate of the upper portion to thereby determine the lengths of the lower portion and upper portion under the same etching conditions.

Claim 4

A field effect transistor comprising: a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type; impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, said impurity layer constituting source.drain regions, and a region between said impurity layers defining a first channel region at said main surface, each of said impurity layers comprising a first impurity layer portion having a first impurity concentration and a second impurity layer portion having a second impurity concentration which is higher than the first impurity concentration, and said first channel region being defined by a first distance between said first impurity layer portions and a second channel region being defined by a second distance between said second impurity layer portions; and a shaped conductive layer formed by etching on said first channel region with an insulating film interposed therebetween at said main surface, said shaped conductive layer having an upper portion and a lower portion, the upper portion begin longer than the lower portion, the length of the lower portion adjacent the insulating film being substantially equal to or shorter than the length of said first channel region, and the upper and lower portions being formed of polysilicon, the upper portion polysilicon of said shaped conductive layer having a first ion impurity therein and the lower portion polysilicon of said shaped conductive layer having a second ion impurity therein, the first and second ion impurities being different elements and being selected so that the lower portion has a faster etch rate as compared with an etch rate of the upper portion to thereby determine the lengths of the lower portion and upper portion under the same etching conditions.