US5675162A
Expired / Lapsed
US
⏱️ 0.0 years remaining
EPROM, flash memory with high coupling ratio
Assignee: United Microelectronics Corp
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Filing: 1996-04-30
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Granted: 1997-10-07
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Expires: 2016-04-30
Abstract
Abstract A semiconductor device is formed on a substrate lightly doped with a dopant, a source region and a drain region in the substrate on the surface thereof, a dielectric layer deposited upon the substrate, a first floating gate layer formed on the dielectric layer, a second floating gate layer formed on the the first floating gate layer, a second dielectric material deposited upon the surface of the first floating gate electrode, a control gate electrode deposited upon the surface of the additional dielectric material, and means for applying a voltage to the control gate electrode.
Inventors
- 👤 Gary Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:53
CPC Classifications
H; H10; H10B; H10B69/00; H10B41/00; H10B41/30
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
187 words
A non-volatile memory device comprising: a substrate having first, second and third field isolation regions formed thereon; a first gate oxide region over the substrate between the first and second field isolation regions; a first floating gate electrode on the first gate oxide region, opposite ends of the first floating gate electrode positioned above the first and second field isolation regions, respectively; first source and drain regions within the substrate and extending between the first and second field isolation regions on either side of the first floating gate electrode; first and second conductive spacers connected to the first floating gate electrode and extending vertically above the first floating gate electrode and the first and second field isolation regions, wherein sides of the first and second conductive spacers are vertically aligned with the opposites edges of the first floating gate electrode positioned over the first and second field isolation regions; a dielectric layer covering the first floating gate electrode and the first and second conductive spacers; and a control electrode overlying the dielectric layer and extending over each vertically extending side of the first and second conductive spacers.
Claim 2
Dependent Claim
187 words
A non-volatile memory device comprising: a substrate having first, second and third field isolation regions formed thereon; a first gate oxide region over the substrate between the first and second field isolation regions; a first floating gate electrode on the first gate oxide region, opposite ends of the first floating gate electrode positioned above the first and second field isolation regions, respectively; first source and drain regions within the substrate and extending between the first and second field isolation regions on either side of the first floating gate electrode; first and second conductive spacers connected to the first floating gate electrode and extending vertically above the first floating gate electrode and the first and second field isolation regions, wherein sides of the first and second conductive spacers are vertically aligned with the opposites edges of the first floating gate electrode positioned over the first and second field isolation regions; a dielectric layer covering the first floating gate electrode and the first and second conductive spacers; and a control electrode overlying the dielectric layer and extending over each vertically extending side of the first and second conductive spacers.
Claim 3
Dependent Claim
38 words
The memory of claim 1, wherein the first floating gate electrode comprises a first layer of polysilicon and wherein the first and second conductive spacers comprise a second layer of polysilicon formed on the first layer of polysilicon.
Claim 4
Dependent Claim
14 words
The memory of claim 2, wherein the field isolation regions are LOCOS oxide structures.
Claim 5
Dependent Claim
101 words
The memory of claim 1, further comprising: a second gate oxide region over the substrate between the second and third field isolation regions; a second floating gate electrode on the second gate oxide region; second source and drain regions within the substrate on either side of the second floating gate electrode; and second conductive spacers connected to the second floating gate electrode and extending vertically above a surface of the second floating gate electrode, wherein the second conductive spacers are covered by the dielectric layer and the control electrode extends above the second floating gate electrode and the second conductive spacers.
Claim 6
Dependent Claim
40 words
The memory of claim 4, wherein a first edge of the first floating gate electrode lies over the second field isolation region and wherein a first edge of the second floating gate electrode lies over the second field isolation region.
Claim 7
Dependent Claim
37 words
The memory of claim 5, wherein a first conductive spacer is adjacent the first edge of the first floating gate electrode and a second conductive spacer is adjacent the first edge of the second floating gate electrode.
Claim 8
Dependent Claim
39 words
The memory of claim 5, wherein a first conductive spacer is aligned with the first edge of the first floating gate electrode and a second conductive spacer is aligned with the first edge of the second floating gate electrode.
Claim 9
Dependent Claim
40 words
The memory of claim 7, wherein the first edge of the first floating gate electrode is separated from the first edge of the second floating gate electrode by a distance less than the design rule used for manufacturing the memory.
Claim 10
Dependent Claim
64 words
The memory of claim 5, wherein a first conductive spacer is aligned with the first edge of the first floating gate electrode and a second conductive spacer is aligned with the first edge of the second floating gate electrode, wherein the dielectric layer extends between the first edge of the first floating gate electrode and the first edge of the second floating gate electrode.
Claim 11
Dependent Claim
20 words
The memory of claim 9, wherein the control electrode extends between the first conductive spacer and the second conductive spacer.
Claim 12
Dependent Claim
14 words
The memory of claim 9, wherein the first and second conductive spacers comprise polysilicon.
References Cited (Backward Citations)
US4812885A
Cited
US5089867A
Cited
US5225362A
Cited
US5293331A
Cited
US5379253A
Cited
US5453393A
Cited
US5281548A
Cited
US5434813A
Cited
US5381028A
Cited
US5389808A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-06 | 2001-04-07 | 2001-10-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-06 | 2005-04-07 | 2005-10-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-06 | 2009-04-07 | 2009-10-07 | $7700.00 | Window Closed / Lapsed |