Abstract An electrically erasable programmable read only memory (EEPROM) cell is fabricated by forming first and second first field oxide (FOX1) regions in a P-well in an N-substrate to define a P-type active device region. First and second buried N+ bit lines are formed in the P-well adjacent to the FOX1 regions; bit lines define a P-type channel region therebetween. First and second second field oxide (FOX2) regions are formed adjacent to the FOX1 regions and overlying the buried N+ bit-lines. A layer of gate oxide 300-500Å thick is formed on the P-well between the FOX2 regions. A layer of polysilicon is formed over the gate oxide to extend over only a first portion of the P-type channel region. A tunnel window is defined on the gate oxide over the P-type channel region and overlapping the floating gate edge. The gate oxide is removed from the tunnel window and tunnel oxide about 80-100Å thick is formed. A spacer/contact window is defined over the field oxide and overlapping the floating gate edge on the field oxide. The edge oxide grown on the floating gate during tunnel oxide growth is removed from the spacer/contact window. A polysilicon tunnel spacer is formed over the tunnel oxide and in electrical contact with the floating gate at the spacer/contact window, i.e. at the floating gate edge over field oxide. Oxide is removed from the top of the floating gate plate and substrate over the channel region and adjacent to the floating gate. Then ONO is grown over the floating gate, the poly tunnel spacer and the exposed channel region adjacent the floating gate. Finally, a second layer polysilicon is formed over the ONO to define a control gate of the EEPROM cell.
A method of fabricating an electrically-erasable programmable read only memory (EEPROM) cell in semiconductor material of P-type conductivity the method comprising: (a) forming first and second spaced-apart first field oxide (FOX1) regions in the P-type semiconductor material to define a P-type active device region therebetween; (b) forming first and second spaced-apart bit lines of N-type conductivity in the P-type semiconductor material adjacent to the first and second FOX1 regions, respectively, such that the first and second bit lines define a P-type channel region therebetween; (c) forming first and second spaced-apart second field oxide (FOX2) regions adjacent to the first and second FOX1 regions, respectively, and overlying the first and second bit lines, respectively; (d) forming a layer of gate dielectric material on the P-type semiconductor material between the first and second FOX2 regions; (e) forming a layer of first conductive material over the gate dielectric material to define a floating gate of the EEPROM cell wherein the layer of first conductive material is formed to extend over only a first portion of the P-type channel region; (f) defining tunnel dielectric material in the gate dielectric material over the P-type channel region such that the thickness of the tunnel dielectric material is less than the thickness of the gate dielectric material; (g) forming a tunnel spacer of first conductive material over the tunnel dielectric and in electrical contact with the floating gate; (h) forming a layer of intermediate dielectric material over the floating gate; and (i) forming a layer of second conductive material over the layer of intermediate dielectric material to define a control gate of the EEPROM cell such that the layer of second conductive material is formed directly on intermediate dielectric material overlying a second portion of the channel region to thereby define the gate of an internal access transistor of the EEPROM cell.
Claim 2
Independent Claim
305 words
A method of fabricating an electrically-erasable programmable read only memory (EEPROM) cell in semiconductor material of P-type conductivity the method comprising: (a) forming first and second spaced-apart first field oxide (FOX1) regions in the P-type semiconductor material to define a P-type active device region therebetween; (b) forming first and second spaced-apart bit lines of N-type conductivity in the P-type semiconductor material adjacent to the first and second FOX1 regions, respectively, such that the first and second bit lines define a P-type channel region therebetween; (c) forming first and second spaced-apart second field oxide (FOX2) regions adjacent to the first and second FOX1 regions, respectively, and overlying the first and second bit lines, respectively; (d) forming a layer of gate dielectric material on the P-type semiconductor material between the first and second FOX2 regions; (e) forming a layer of first conductive material over the gate dielectric material to define a floating gate of the EEPROM cell wherein the layer of first conductive material is formed to extend over only a first portion of the P-type channel region; (f) defining tunnel dielectric material in the gate dielectric material over the P-type channel region such that the thickness of the tunnel dielectric material is less than the thickness of the gate dielectric material; (g) forming a tunnel spacer of first conductive material over the tunnel dielectric and in electrical contact with the floating gate; (h) forming a layer of intermediate dielectric material over the floating gate; and (i) forming a layer of second conductive material over the layer of intermediate dielectric material to define a control gate of the EEPROM cell such that the layer of second conductive material is formed directly on intermediate dielectric material overlying a second portion of the channel region to thereby define the gate of an internal access transistor of the EEPROM cell.
Claim 3
Dependent Claim
19 words
A method as in claim 1 wherein the tunnel dielectric material and the gate dielectric material comprise silicon dioxide.
Claim 4
Dependent Claim
13 words
A method as in claim 2 wherein the first conductive material comprises polysilicon.
Claim 5
Dependent Claim
15 words
A method as in claim 3 wherein the intermediate dielectric material comprises an oxide/nitride/oxide composite.
Claim 6
Dependent Claim
13 words
A method as in claim 4 wherein the second conductive material comprises polysilicon.
Claim 7
Dependent Claim
17 words
A method as in claim 5 wherein the second conductive material comprises polysilicon and overlying tungsten silicide.
Claim 8
Dependent Claim
25 words
A method as in claim 1 wherein the P-type semiconductor material comprises a well of P-type conductivity formed in a silicon substrate of N-type conductivity.