US5952694A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device made using processing from both sides of a workpiece
Assignee: Canon Inc
•
Filing: 1995-03-14
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Granted: 1999-09-14
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Expires: 2015-03-14
Abstract
Abstract A semiconductor device having a semiconductor layer formed on a substrate having an insulating surface, comprises a first region formed by processing the semiconductor layer from one major surface thereof, and a second region formed by processing the semiconductor layer from the other major surface, the first and second regions cooperating to constitute a semiconductor function element, isolation region or the like.
Inventors
- 👤 Mamoru Miyawaki
- 👤 Yasushi Kawasumi
- 👤 Shunsuke Inoue
- 👤 Yutaka Akino
- 👤 Toru Koizumi
- 👤 Tetsunobu Kohchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 03:45
CPC Classifications
H; H10; H10P; H10P36/00; H10P36/03; H10P36/07; H10D; H10D86/00; H10D86/201; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10W46/00; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10P90/1914; H10W10/011; H10W10/012; H10W10/014; H10W10/041; H10W10/13; H10W10/17; H10W10/40; H10W46/101; H10W46/301; H10W46/501
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
136 words
A semiconductor device comprising: a substrate having an insulating surface; insulating regions disposed on at least a portion of the insulating surface; a semiconductor layer disposed on at least a portion of the insulating surface and said insulating regions, said semiconductor layer having a plurality of function elements disposed therein; and an upper insulating layer disposed on said semiconductor layer, said upper insulating layer having a plurality of insulating extension portions, each of the insulating extension portions being substantially vertically aligned with and spaced from a respective one of said insulating regions, and being separated from the respective one of said insulating regions by a portion of said semiconductor layer, wherein at least some of said function elements are substantially isolated from others of said functional elements by said insulating extension portions and said insulating regions.
Claim 2
Dependent Claim
136 words
A semiconductor device comprising: a substrate having an insulating surface; insulating regions disposed on at least a portion of the insulating surface; a semiconductor layer disposed on at least a portion of the insulating surface and said insulating regions, said semiconductor layer having a plurality of function elements disposed therein; and an upper insulating layer disposed on said semiconductor layer, said upper insulating layer having a plurality of insulating extension portions, each of the insulating extension portions being substantially vertically aligned with and spaced from a respective one of said insulating regions, and being separated from the respective one of said insulating regions by a portion of said semiconductor layer, wherein at least some of said function elements are substantially isolated from others of said functional elements by said insulating extension portions and said insulating regions.
Claim 3
Dependent Claim
49 words
A semiconductor device according to claim 1, wherein at least one of said function elements includes an n+ layer that is in contact with said insulating surface, and wherein at least another one of said function elements includes a p+ layer that is in contact with said insulating surface.
Claim 4
Dependent Claim
22 words
A semiconductor device according to claim 1, wherein said substrate comprises a semiconductor material, and said insulating surface comprises an insulating film.
Claim 5
Dependent Claim
32 words
A semiconductor device according to claim 1, wherein said semiconductor layer has a greater thickness than each of the plurality of insulating extension portions and each of the plurality of insulating regions.
References Cited (Backward Citations)
US3767304A
Cited
DE2832152A1
Cited
US4238760A
Cited
US4261003A
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JPS6031274A
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US4677735A
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US4755862A
Cited
US4710794A
Cited
US4984033A
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EP0256397A1
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US4875086A
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US5043785A
Cited
US4979006A
Cited
US5173446A
Cited
US5459346A
Cited
US4968628A
Cited
US5004705A
Cited
US5043782A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-13 | 2003-03-15 | 2003-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-13 | 2007-03-15 | 2007-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-13 | 2011-03-15 | 2011-09-14 | $7700.00 | Window Closed / Lapsed |