Method for constructing multiple container capacitor

Claim 1

A method for providing a conductive bottom electrode for an integrated capacitor, the method comprising: forming a first conductive layer over a structural layer formed over a semiconductor substrate; forming a via through the first conductive layer and the structural layer, the via having a substantially vertical sidewall; depositing a second conductive layer over the first conductive layer and into the via; forming a sidewall spacer over the second conductive layer at the via sidewall; performing a contact etch through an insulating layer underlying the structural layer, the contact etch extending the via downward to expose an active area within the semiconductor substrate; depositing a third conductive layer over the structural layer and into the extended via, the third conductive layer forming electrical contact with the active area and with the second conductive layer; planarizing the structural layer below portions of the conductive layers overlying the structural layer; and substantially removing the structural layer and the sidewall spacer.

Claim 2

A method for providing a conductive bottom electrode for an integrated capacitor, the method comprising: forming a first conductive layer over a structural layer formed over a semiconductor substrate; forming a via through the first conductive layer and the structural layer, the via having a substantially vertical sidewall; depositing a second conductive layer over the first conductive layer and into the via; forming a sidewall spacer over the second conductive layer at the via sidewall; performing a contact etch through an insulating layer underlying the structural layer, the contact etch extending the via downward to expose an active area within the semiconductor substrate; depositing a third conductive layer over the structural layer and into the extended via, the third conductive layer forming electrical contact with the active area and with the second conductive layer; planarizing the structural layer below portions of the conductive layers overlying the structural layer; and substantially removing the structural layer and the sidewall spacer.

Claim 24

A method of forming a bottom electrode for an integrated container capacitor over a circuit node, the method comprising: forming a conductive outer container within a structural layer overlying an insulating layer; forming a spacer around an outer container sidewall; performing a contact etch through a bottom of the outer container and through the insulating layer to expose the circuit node; forming a conductive inner container in electrical contact with the circuit node and with the outer container, an inner container sidewall separated from the outer container sidewall by the spacer.

Claim 25

A method of forming a bottom electrode for an integrated container capacitor over a circuit node, the method comprising: forming a conductive outer container within a structural layer overlying an insulating layer; forming a spacer around an outer container sidewall; performing a contact etch through a bottom of the outer container and through the insulating layer to expose the circuit node; forming a conductive inner container in electrical contact with the circuit node and with the outer container, an inner container sidewall separated from the outer container sidewall by the spacer.

Claim 32

A method of providing a conductive bottom electrode for an integrated capacitor, the method comprising: forming a conductive outer container within a structural layer overlying an insulating layer; forming a spacer around an outer container sidewall; performing a contact etch through a bottom of the outer container and through the insulating layer to expose a circuit node; forming a conductive inner container in electrical contact with the circuit node and with the outer container, an inner container sidewall separated from the outer container sidewall by the spacer; planarizing the inner and outer containers; and selectively removing the spacer from between the containers.

Claim 33

A method of providing a conductive bottom electrode for an integrated capacitor, the method comprising: forming a conductive outer container within a structural layer overlying an insulating layer; forming a spacer around an outer container sidewall; performing a contact etch through a bottom of the outer container and through the insulating layer to expose a circuit node; forming a conductive inner container in electrical contact with the circuit node and with the outer container, an inner container sidewall separated from the outer container sidewall by the spacer; planarizing the inner and outer containers; and selectively removing the spacer from between the containers.

Claim 35

A method for providing a conductive bottom electrode for an integrated capacitor, the method comprising: providing a pair of word lines insulated by silicon nitride above a semiconductor substrate; forming a first oxide layer over the insulated word lines; forming a thin silicon nitride layer over the oxide layer; forming a second oxide layer over the silicon nitride layer; depositing a first polysilicon layer over the second oxide layer; anisotropically etching a via through the first polysilicon layer and the second oxide layer, the via etch forming a substantially vertical via sidewall and stopping at the silicon nitride layer; forming a conductively doped second polysilicon layer into the via and over the second first polysilicon layer; forming a layer of second silicon nitride layer over the second polysilicon layer, performing a spacer etch on the second silicon nitride layer to form a nitride spacer adjacent a vertical portion of the second polysilicon layer within the via and covering a horizontal bottom portion of the second polysilicon layer proximate the via sidewall while exposing a bottom portion of the second polysilicon layer proximate a via center; performing a contact etch through an exposed via bottom portion of the second polysilicon, through the first silicon nitride layer, and through the first oxide layer between the insulated word lines, the contact etch extending the via to expose the semiconductor substrate; forming a conductively doped third polysilicon layer into the extended via and superjacent the spacer, the third polysilicon layer in electrical contact with both the semiconductor substrate and the second conductive layer; filling the via with photoresist after forming the third polysilicon layer; performing a chemical mechanical planarization on the integrated circuit; and selectively removing the spacer, photoresist and second oxide layer.

Claim 36

A method for providing a conductive bottom electrode for an integrated capacitor, the method comprising: providing a pair of word lines insulated by silicon nitride above a semiconductor substrate; forming a first oxide layer over the insulated word lines; forming a thin silicon nitride layer over the oxide layer; forming a second oxide layer over the silicon nitride layer; depositing a first polysilicon layer over the second oxide layer; anisotropically etching a via through the first polysilicon layer and the second oxide layer, the via etch forming a substantially vertical via sidewall and stopping at the silicon nitride layer; forming a conductively doped second polysilicon layer into the via and over the second first polysilicon layer; forming a layer of second silicon nitride layer over the second polysilicon layer, performing a spacer etch on the second silicon nitride layer to form a nitride spacer adjacent a vertical portion of the second polysilicon layer within the via and covering a horizontal bottom portion of the second polysilicon layer proximate the via sidewall while exposing a bottom portion of the second polysilicon layer proximate a via center; performing a contact etch through an exposed via bottom portion of the second polysilicon, through the first silicon nitride layer, and through the first oxide layer between the insulated word lines, the contact etch extending the via to expose the semiconductor substrate; forming a conductively doped third polysilicon layer into the extended via and superjacent the spacer, the third polysilicon layer in electrical contact with both the semiconductor substrate and the second conductive layer; filling the via with photoresist after forming the third polysilicon layer; performing a chemical mechanical planarization on the integrated circuit; and selectively removing the spacer, photoresist and second oxide layer.