Patent US5930677A successfully refreshed from Google Patents.
US5930677A
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Method for reducing microloading in an etchback of spin-on-glass or polymer
Assignee: GlobalFoundries Singapore Pte Ltd
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Filing: 1997-04-21
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Granted: 1999-07-27
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Expires: 2017-04-21
Abstract
Abstract A method for forming a planarized interlevel dielectric layer without degradation due to the microloading effect from spin-on material etchback is described. A patterned first conducting layer is provided over an insulating layer on a semiconductor substrate. An improved interlevel dielectric layer is formed overlying the patterned first conducting layer by the following steps. A first oxide layer is deposited overlying the patterned first conducting layer and the insulating layer. A spin-on material layer is coated overlying the first oxide layer and etched back using O 2 gas added to the CHF 3 /CF 4 chemistry until the first oxide layer is exposed overlying the patterned first conducting layer wherein microloading effects from the etching back of the spin-on material layer are lower than microloading effects in a conventional interlevel dielectric layer. A second oxide layer is deposited to complete the interlevel dielectric layer. A second conducting layer is deposited over the interlevel dielectric layer and patterned to complete the fabrication of the integrated circuit device.
Inventors
- 👤 Jia Zhen Zheng
- 👤 Guo Li Qi Mike
- 👤 Yi Xu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:43
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/63; H10P14/6326; H10P14/6342; H10P14/66; H10P14/662; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/69215
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
190 words
A method of fabricating an integrated circuit device comprising: providing a patterned first conducting layer over an insulating layer on a semiconductor substrate; forming an interlevel dielectric layer overlying said patterned first conducting layer by the steps of: depositing a first oxide layer overlying said patterned first conducting layer and said insulating layer; coating a spin-on material layer overlying said first oxide layer; etching back said spin-on material layer using a plasma etch to which O 2 gas has been added in the amount of 2 to 30 sccm until said first oxide layer is exposed overlying said patterned first conducting layer wherein because of the presence of said O 2 gas, the additional release of oxygen from said exposed first oxide layer will not increase the etching rate of said spin-on material whereby microloading effects from said etching back of said spin-on material layer are reduced; and depositing a second oxide layer overlying said spin-on material layer and said exposed first oxide layer; depositing a second conducting layer over said improved interlevel dielectric layer; and patterning said second conducting layer to complete the fabrication of said integrated circuit device.
Claim 2
Independent Claim
190 words
A method of fabricating an integrated circuit device comprising: providing a patterned first conducting layer over an insulating layer on a semiconductor substrate; forming an interlevel dielectric layer overlying said patterned first conducting layer by the steps of: depositing a first oxide layer overlying said patterned first conducting layer and said insulating layer; coating a spin-on material layer overlying said first oxide layer; etching back said spin-on material layer using a plasma etch to which O 2 gas has been added in the amount of 2 to 30 sccm until said first oxide layer is exposed overlying said patterned first conducting layer wherein because of the presence of said O 2 gas, the additional release of oxygen from said exposed first oxide layer will not increase the etching rate of said spin-on material whereby microloading effects from said etching back of said spin-on material layer are reduced; and depositing a second oxide layer overlying said spin-on material layer and said exposed first oxide layer; depositing a second conducting layer over said improved interlevel dielectric layer; and patterning said second conducting layer to complete the fabrication of said integrated circuit device.
Claim 3
Dependent Claim
28 words
The method according to claim 1 wherein said semiconductor substrate comprises semiconductor device structures including gate electrodes and source and drain regions in and on a silicon substrate.
Claim 4
Dependent Claim
24 words
The method according to claim 1 wherein said first oxide layer comprises silicon oxide having a thickness of between about 500 and 5000 Angstroms.
Claim 5
Dependent Claim
33 words
The method according to claim 1 wherein said first oxide layer comprises tetraethoxysilane (TEOS) oxide deposited by plasma enhanced chemical vapor deposition (PECVD) to a thickness of between about 500 and 5000 Angstroms.
Claim 6
Dependent Claim
31 words
The method according to claim 1 wherein said first oxide layer comprises silane oxide deposited by plasma enhanced chemical vapor deposition to a thickness of between about 500 and 5000 Angstroms.
Claim 7
Dependent Claim
26 words
The method according to claim 1 wherein said first oxide layer comprises high density plasma oxide having a thickness of between about 500 and 5000 Angstroms.
Claim 8
Dependent Claim
24 words
The method according to claim 1 wherein said spin-on material layer comprises spin-on-glass coated to a thickness of between about 1000 and 8000 Angstroms.
Claim 9
Dependent Claim
25 words
The method according to claim 1 wherein said spin-on material layer comprises a spin-on-polymer coated to a thickness of between about 1000 and 8000 Angstroms.
Claim 10
Dependent Claim
12 words
The method according to claim 8 wherein said spin-on-polymer comprises methyl silsesquioxane.
Claim 11
Dependent Claim
12 words
The method according to claim 8 wherein said spin-on-polymer comprises methyl siloxane.
Claim 12
Dependent Claim
58 words
The method according to claim 1 wherein said etching back of said spin-on material layer is done using a CHF 3 and CF 4 plasma etch to which O 2 gas has been added in the amount of 2 to 30 sccm at a temperature of 30 to 200° C. for a duration of 30 to 90 seconds.
Claim 13
Dependent Claim
29 words
The method according to claim 1 wherein said second oxide layer comprises TEOS oxide and is deposited by PECVD to a thickness of between about 3000 and 20,000 Angstroms.
Claim 14
Dependent Claim
29 words
The method according to claim 1 wherein said second oxide layer comprises silane oxide and is deposited by PECVD to a thickness of between about 3000 and 20,000 Angstroms.
Claim 15
Independent Claim
208 words
A method of fabricating an integrated circuit device comprising: providing a patterned first conducting layer over an insulating layer on a semiconductor substrate; forming an interlevel dielectric layer overlying said patterned first conducting layer by the steps of: depositing a first oxide layer overlying said patterned first conducting layer and said insulating layer; coating a spin-on material layer overlying said first oxide layer; etching back said spin-on material layer using CHF 3 and CF 4 plasma with O 2 gas until said first oxide layer is exposed overlying said patterned first conducting layer wherein because of the presence of said O 2 gas, the additional release of oxygen from said exposed first oxide layer will not increase the etching rate of said spin-on material whereby microloading effects from said etching back of said spin-on material layer are reduced and wherein after said etching back of said spin-on material layer said spin-on-material layer and said exposed first oxide layer form a planarized surface; and depositing a second oxide layer overlying said planarized surface of said spin-on material layer and said exposed first oxide layer; depositing a second conducting layer over said interlevel dielectric layer; and patterning said second conducting layer to complete the fabrication of said integrated circuit device.
Claim 16
Independent Claim
208 words
A method of fabricating an integrated circuit device comprising: providing a patterned first conducting layer over an insulating layer on a semiconductor substrate; forming an interlevel dielectric layer overlying said patterned first conducting layer by the steps of: depositing a first oxide layer overlying said patterned first conducting layer and said insulating layer; coating a spin-on material layer overlying said first oxide layer; etching back said spin-on material layer using CHF 3 and CF 4 plasma with O 2 gas until said first oxide layer is exposed overlying said patterned first conducting layer wherein because of the presence of said O 2 gas, the additional release of oxygen from said exposed first oxide layer will not increase the etching rate of said spin-on material whereby microloading effects from said etching back of said spin-on material layer are reduced and wherein after said etching back of said spin-on material layer said spin-on-material layer and said exposed first oxide layer form a planarized surface; and depositing a second oxide layer overlying said planarized surface of said spin-on material layer and said exposed first oxide layer; depositing a second conducting layer over said interlevel dielectric layer; and patterning said second conducting layer to complete the fabrication of said integrated circuit device.
Claim 17
Dependent Claim
28 words
The method according to claim 14 wherein said semiconductor substrate comprises semiconductor device structures including gate electrodes and source and drain regions in and on a silicon substrate.
Claim 18
Dependent Claim
22 words
The method according to claim 14 wherein said semiconductor substrate comprises a level of metallization lower than said first patterned conducting layer.
Claim 19
Dependent Claim
21 words
The method according to claim 14 wherein said first oxide layer has a thickness of between about 500 and 5000 Angstroms.
Claim 20
Dependent Claim
24 words
The method according to claim 14 wherein said spin-on material layer comprises spin-on-glass coated to a thickness of between about 1000 and 8000 Angstroms.
Claim 21
Dependent Claim
25 words
The method according to claim 14 wherein said spin-on material layer comprises a spin-on-polymer coated to a thickness of between about 1000 and 8000 Angstroms.
Claim 22
Dependent Claim
59 words
The method according to claim 14 wherein said etching back of said spin-on material layer is done using said CHF 3 and CF 4 plasma etch to which said O 2 gas has been added in the amount of 2 to 30 sccm at a temperature of 30 to 200° C. for a duration of 30 to 90 seconds.
Claim 23
Dependent Claim
29 words
The method according to claim 14 wherein said second oxide layer comprises TEOS oxide and is deposited by PECVD to a thickness of between about 3000 and 20,000 Angstroms.
Claim 24
Dependent Claim
29 words
The method according to claim 14 wherein said second oxide layer comprises silane oxide and is deposited by PECVD to a thickness of between about 3000 and 20,000 Angstroms.
Claim 25
Independent Claim
196 words
A method of fabricating a planarized and improved interlevel dielectric layer in an integrated circuit device comprising: providing a patterned first conducting layer over an insulating layer on a semiconductor substrate; depositing a first oxide layer overlying said patterned first conducting layer and said insulating layer; coating a spin-on material layer overlying said first oxide layer; etching back said spin-on material layer using a plasma etch to which O 2 gas is added until said first oxide layer is exposed overlying said patterned first conducting layer wherein because of the presence of said O 2 gas, the additional release of oxygen from said exposed first oxide layer will not increase the etching rate of said spin-on material whereby microloading effects from said etching back of said spin-on material layer are reduced and wherein after said etching back of said spin-on material layer, said spin-on-material layer and said exposed first oxide layer form a planarized surface; and depositing a second oxide layer overlying said planarized surface of said spin-on material layer and said exposed first oxide layer to complete the formation of said planarized and improved interlevel dielectric layer in the fabrication of said integrated circuit device.
Claim 26
Independent Claim
196 words
A method of fabricating a planarized and improved interlevel dielectric layer in an integrated circuit device comprising: providing a patterned first conducting layer over an insulating layer on a semiconductor substrate; depositing a first oxide layer overlying said patterned first conducting layer and said insulating layer; coating a spin-on material layer overlying said first oxide layer; etching back said spin-on material layer using a plasma etch to which O 2 gas is added until said first oxide layer is exposed overlying said patterned first conducting layer wherein because of the presence of said O 2 gas, the additional release of oxygen from said exposed first oxide layer will not increase the etching rate of said spin-on material whereby microloading effects from said etching back of said spin-on material layer are reduced and wherein after said etching back of said spin-on material layer, said spin-on-material layer and said exposed first oxide layer form a planarized surface; and depositing a second oxide layer overlying said planarized surface of said spin-on material layer and said exposed first oxide layer to complete the formation of said planarized and improved interlevel dielectric layer in the fabrication of said integrated circuit device.
Claim 27
Dependent Claim
21 words
The method according to claim 23 wherein said first oxide layer has a thickness of between about 500 and 5000 Angstroms.
Claim 28
Dependent Claim
24 words
The method according to claim 23 wherein said spin-on material layer comprises spin-on-glass coated to a thickness of between about 1000 and 8000 Angstroms.
Claim 29
Dependent Claim
25 words
The method according to claim 23 wherein said spin-on material layer comprises a spin-on-polymer coated to a thickness of between about 1000 and 8000 Angstroms.
Claim 30
Dependent Claim
62 words
The method according to claim 23 wherein said etching back of said spin-on material layer is done using CHF 3 and CF 4 plasma in a ratio of 4:40 to which said O 2 gas has been added in the amount of 2 to 30 sccm at a temperature of 30 to 200° C. for a duration of 30 to 90 seconds.
Claim 31
Dependent Claim
29 words
The method according to claim 23 wherein said second oxide layer comprises TEOS oxide and is deposited by PECVD to a thickness of between about 3000 and 20,000 Angstroms.
Claim 32
Dependent Claim
29 words
The method according to claim 23 wherein said second oxide layer comprises silane oxide and is deposited by PECVD to a thickness of between about 3000 and 20,000 Angstroms.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-07-26 | 2003-01-25 | 2003-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-26 | 2007-01-25 | 2007-07-27 | $3760.00 | Window Closed / Lapsed |
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