Abstract A method of forming a field effect transistor includes, a) providing a gate over a semiconductor substrate, the gate having a thickness; b) providing an insulating dielectric layer over the gate, the insulating dielectric layer being provided to a thickness which is greater than the gate thickness to provide an outer dielectric layer surface which is above the gate; c) patterning and etching the insulating dielectric layer to provide openings therethrough to the substrate to define and expose active area adjacent the gate for formation of one of PMOS type or NMOS type diffusion regions; d) providing a layer of conductive material over the insulating dielectric layer and within the openings; e) providing the one of PMOS or NMOS type diffusion regions within the substrate relative to the first openings; and f) etching back the conductive layer to define electrically conductive projections which are isolated from one another within the openings. The method has specific applicability to CMOS fabrication, and provision of overlying and differently conductively doped polysilicon layers which are chemical-mechanical polished in a common step.
A method of forming CMOS integrated circuitry comprising the following steps: providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to the substrate for formation of an NMOS transistor, a second gate line being positioned relative to the substrate for formation of a PMOS transistor; forming an insulating dielectric layer over the gate lines, the insulating dielectric layer being provided to a thickness effective to provide an outer dielectric layer surface which is above the first and second gate lines, the insulating dielectric layer comprising BPSG; forming first openings through the insulating dielectric layer to adjacent one of the first or second gate lines for formation of one of PMOS type or NMOS type diffusion regions; forming a first layer of conductive material over the insulating dielectric layer and within the first openings; forming the one of PMOS or NMOS type diffusion regions within the substrate relative to the first openings; forming second openings through both of the first layer of conductive material and the underlying insulating dielectric layer to adjacent the other of the first or second gate lines for formation of the other of PMOS type or NMOS type diffusion regions; forming a second layer of conductive material over the first layer of conductive material and within the second openings; and forming the other of PMOS or NMOS type diffusion regions within the substrate relative to the second openings.
Claim 2
Independent Claim
239 words
A method of forming CMOS integrated circuitry comprising the following steps: providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to the substrate for formation of an NMOS transistor, a second gate line being positioned relative to the substrate for formation of a PMOS transistor; forming an insulating dielectric layer over the gate lines, the insulating dielectric layer being provided to a thickness effective to provide an outer dielectric layer surface which is above the first and second gate lines, the insulating dielectric layer comprising BPSG; forming first openings through the insulating dielectric layer to adjacent one of the first or second gate lines for formation of one of PMOS type or NMOS type diffusion regions; forming a first layer of conductive material over the insulating dielectric layer and within the first openings; forming the one of PMOS or NMOS type diffusion regions within the substrate relative to the first openings; forming second openings through both of the first layer of conductive material and the underlying insulating dielectric layer to adjacent the other of the first or second gate lines for formation of the other of PMOS type or NMOS type diffusion regions; forming a second layer of conductive material over the first layer of conductive material and within the second openings; and forming the other of PMOS or NMOS type diffusion regions within the substrate relative to the second openings.