Programmable logic array circuits comprising look up table implementation of fast carry adders and counters

Abstract

Abstract A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors. Look up tables for use in programmable logic devices are modified to facilitate use of those tables to provide adders (including subtracters) and various types of counters. Each look up table is effectively partitioned into smaller look up tables when an adder or counter is required. One portion of the partitioned table is used to provide a sum out signal, while the other portion of the partitioned table is used to provide a fast carry out signal for application to the next stage of the adder or counter.

Inventors

• 👤 Richard G. Cliff
• 👤 L. Todd Cope
• 👤 Kerry Veenstra
• 👤 Bruce B. Pedersen

Bibliographic Details