Patent US5923983A successfully refreshed from Google Patents.
US5923983A
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Integrated circuit gate conductor having a gate dielectric which is substantially resistant to hot carrier effects
Assignee: Advanced Micro Devices Inc
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Filing: 1996-12-23
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Granted: 1999-07-13
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Expires: 2016-12-23
Abstract
Abstract An integrated circuit is formed whereby transistor gate dielectrics are made less susceptible to hot carrier effects. Barrier atoms are inserted into critical areas to minimize trapping of hot carriers within the gate dielectric. Barrier atoms are incorporated into critical areas within the gate dielectric, primarily at the juncture between the gate dielectric and the overlying gate conductor and underlying substrate. The barrier atoms serve to eliminate bond opportunities of hot carriers injected from the drain area. The barrier atoms are presented by elevating the temperature of the integrated circuit being produced and the barrier-embodied gas surrounding the circuit. The elevated temperatures occur within either an RTA furnace or an oxidizing furnace. Significant is the incorporation of barrier atoms during a normal process flow, either during polysilicon oxidation and/or implant anneal. According to one embodiment, barrier atoms are incorporated after the LDD implant during times in which a polysilicon oxide is grown. According to a second embodiment, barrier atoms are incorporated after the source/drain implant and during anneal of those implant species. In yet another embodiment, barrier atoms are incorporated during each of the above steps.
Inventors
- 👤 H. Jim Fulford, Jr.
- 👤 Mark I. Gardner
- 👤 Derick J. Wristers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 19:39
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01338; H10D64/01354; H10D64/60; H10D64/66; H10D64/671; H10D64/68; H10D64/693
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
103 words
A method for forming an integrated circuit, comprising: growing a gate dielectric upon a semiconductor substrate; patterning a gate conductor to have exposed sidewall surfaces opposed across a portion of said gate dielectric; growing an oxide in the presence of first barrier atoms to a first defined thickness upon said exposed sidewall surfaces; forming a spacer to a second defined thickness upon said oxide; using said gate conductor, said oxide, and said spacer as a mask, implanting a source area and a drain area into said semiconductor substrate; and subsequent said implanting, annealing said semiconductor substrate in the presence of second barrier atoms.
Claim 2
Independent Claim
103 words
A method for forming an integrated circuit, comprising: growing a gate dielectric upon a semiconductor substrate; patterning a gate conductor to have exposed sidewall surfaces opposed across a portion of said gate dielectric; growing an oxide in the presence of first barrier atoms to a first defined thickness upon said exposed sidewall surfaces; forming a spacer to a second defined thickness upon said oxide; using said gate conductor, said oxide, and said spacer as a mask, implanting a source area and a drain area into said semiconductor substrate; and subsequent said implanting, annealing said semiconductor substrate in the presence of second barrier atoms.
Claim 3
Dependent Claim
30 words
The method as recited in claim 1 wherein said growing said oxide comprises introducing said barrier atoms into said gate dielectric proximate to said sidewall surfaces of said gate conductor.
Claim 4
Dependent Claim
24 words
The method as recited in claim 1 wherein said growing said oxide comprises heating said gate conductor in the presence of a nitrogen-bearing gas.
Claim 5
Dependent Claim
30 words
The method as recited in claim 3 wherein said growing said oxide further comprises introducing said nitrogen into said gate dielectric proximate to said sidewall surfaces of said gate conductor.
Claim 6
Dependent Claim
33 words
The method as recited in claim 1, said annealing comprising forwarding said second barrier atoms through said spacer into said gate dielectric proximate to one of said sidewall surfaces of said gate conductor.
Claim 7
Dependent Claim
22 words
The method as recited in claim 1 wherein said first barrier atoms and said second barrier atoms comprise the same chemical element.
Claim 8
Dependent Claim
13 words
The method as recited in claim 6 wherein said chemical element is nitrogen.
Claim 9
Dependent Claim
21 words
The method as recited in claim 1 wherein said first barrier atoms and said second barrier atoms comprise different chemical elements.
Claim 10
Dependent Claim
15 words
The method as recited in claim 8 wherein one of said chemical elements is nitrogen.
Claim 11
Dependent Claim
51 words
The method as recited in claim 1 wherein said implanting a source area and a drain area comprises implanting a first dopant into said semiconductor substrate a first spaced distance form said sidewall surfaces, said first spaced distance being substantially equal to a combined thickness of said spacer and said oxide.
Claim 12
Dependent Claim
62 words
The method as recited in claim 10, further comprising forming a lightly doped drain area prior to forming said spacer, wherein said forming comprises implanting a second dopant of lesser concentration and energy than said first dopant into said semiconductor substrate a second spaced distance from said sidewall surfaces, said second spaced distance being substantially equal to the thickness of said oxide.
Claim 13
Dependent Claim
19 words
The method as recited in claim 1 wherein said gate conductor is patterned from a layer of polycrystalline silicon.
Claim 14
Dependent Claim
41 words
The method as recited in claim 1 wherein said forming a spacer comprises: depositing a layer of nitride upon said oxide; and anisotropically removing said layer of nitride except upon the oxide arranged immediately adjacent sidewall surfaces of said gate conductor.
Claim 15
Dependent Claim
55 words
The method as recited in claim 1 wherein said annealing comprises heating said semiconductor topography simultaneously with forwarding a plurality of nitrogen atoms from a nitrogen-bearing ambient through said spacer and into an area of the gate dielectric beneath one of said sidewall surfaces to minimize the number of hot carriers entering said gate dielectric.
Claim 16
Dependent Claim
38 words
The method as recited in claim 14 wherein a predominant portion of said nitrogen atoms bond with oxygen atoms within said gate dielectric near the interface between said gate dielectric and a lateral perimeter of said gate conductor.
Claim 17
Independent Claim
108 words
A method for forming an integrated circuit, comprising: growing a gate dielectric upon a semiconductor substrate; patterning a gate conductor between opposed sidewall surfaces across a portion of said gate dielectric; growing an oxide to a first defined thickness upon said sidewall surfaces; forming a spacer to a second defined thickness upon said oxide; using said gate conductor and said spacer as a mask, implanting a source area and a drain area into said semiconductor substrate; and subsequent to said implanting said source area and said drain area, annealing said semiconductor substrate in the presence of a barrier-entrained gas, wherein said barrier-entrained gas comprises barrier atoms and oxygen.
Claim 18
Independent Claim
108 words
A method for forming an integrated circuit, comprising: growing a gate dielectric upon a semiconductor substrate; patterning a gate conductor between opposed sidewall surfaces across a portion of said gate dielectric; growing an oxide to a first defined thickness upon said sidewall surfaces; forming a spacer to a second defined thickness upon said oxide; using said gate conductor and said spacer as a mask, implanting a source area and a drain area into said semiconductor substrate; and subsequent to said implanting said source area and said drain area, annealing said semiconductor substrate in the presence of a barrier-entrained gas, wherein said barrier-entrained gas comprises barrier atoms and oxygen.
Claim 19
Dependent Claim
20 words
The method as recited in claim 16, further comprising forming a lightly doped drain area prior to forming said spacer.
Claim 20
Dependent Claim
96 words
The method as recited in claim 17, said implanting a source area and a drain area comprising implanting a first dopant into said semiconductor substrate a first spaced distance from said sidewall surfaces, said first spaced distance being substantially equal to a combined thickness of said spacer and said oxide, said forming a lightly doped drain area comprising implanting a second dopant of lesser concentration and energy than said first dopant into said semiconductor substrate a second spaced distance from said sidewall surfaces, said second spaced distance being substantially equal to a thickness of said oxide.
Claim 21
Dependent Claim
13 words
The method as recited in claim 17 wherein said barrier atoms comprise nitrogen.
Claim 22
Dependent Claim
19 words
The method as recited in claim 16 wherein said gate conductor is patterned from a layer of polycrystalline silicon.
Claim 23
Dependent Claim
41 words
The method as recited in claim 16 wherein said forming a spacer comprises: depositing a layer of nitride upon said oxide; and anisotropically removing said layer of nitride except upon the oxide arranged immediately adjacent sidewall surfaces of said gate conductor.
Claim 24
Dependent Claim
53 words
The method as recited in claim 16 wherein said annealing comprises heating said semiconductor topography simultaneous with forwarding a plurality of nitrogen atoms from said barrier-entrained gas through said spacer and into an area of the gate dielectric beneath one of said sidewall surfaces to minimize hot carriers from entering said gate dielectric.
Claim 25
Dependent Claim
38 words
The method as recited in claim 22 wherein a predominant portion of said nitrogen atoms bond with oxygen atoms within said gate dielectric near the interface between said gate dielectric and a lateral perimeter of said gate conductor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-12 | 2003-01-11 | 2003-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-12 | 2007-01-11 | 2007-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-12 | 2011-01-11 | 2011-07-13 | $7700.00 | Window Closed / Lapsed |