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US5827769A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode

Assignee: Intel Corp
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Filing: 1996-11-20
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Granted: 1998-10-27
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Expires: 2016-11-20
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Abstract

Abstract A method of fabricating a field effect transistor with increased resistance to hot carrier damage is disclosed. An oxide is grown on the gate electrode. This oxide is strengthened by nitridation and anneal. After a lightly doped drain implant, a second side oxide and a conformal nitride layer are deposited. Then, the conformal nitride is anisotropically etched to form spacers for masking a high dose drain implant. An NMOS transitor fabricated with this process has been found to be forty percent less susceptible to hot carrier damage than a conventional lightly doped drain process. Also, this process has proven to be more manufacturable than one in which the side oxide is nitrided and re-oxidized.

Inventors

  • 👤 Payman Aminzadeh
  • 👤 Reza Arghavani
  • 👤 Peter Moon

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 19:52
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/021; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/60; H10D64/66; H10D64/671; H10P; H10P14/00; H10P14/60; H10P14/66; H10P14/662

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 94 words
A method of fabricating a field effect transistor comprising the steps of: forming a gate electrode; forming a first oxide on the sidewalls of said gate electrode; nitridating said first oxide to create a nitrided oxide; annealing said nitrided oxide to create an annealed nitrided oxides; forming a second oxide adjacent to said annealed nitrided oxide; forming a conformal layer over said gate electrode, said annealed nitrided oxide, and said second oxide; and anisotropically etching said conformal layer to create spacers for masking a lightly doped drain region from a high dose drain implant.
Claim 2
Independent Claim 94 words
A method of fabricating a field effect transistor comprising the steps of: forming a gate electrode; forming a first oxide on the sidewalls of said gate electrode; nitridating said first oxide to create a nitrided oxide; annealing said nitrided oxide to create an annealed nitrided oxides; forming a second oxide adjacent to said annealed nitrided oxide; forming a conformal layer over said gate electrode, said annealed nitrided oxide, and said second oxide; and anisotropically etching said conformal layer to create spacers for masking a lightly doped drain region from a high dose drain implant.
Claim 3
Dependent Claim 14 words
The method of claim 1 wherein said first oxide is formed by dry oxidation.
Claim 4
Dependent Claim 16 words
The method of claim 1 wherein said first oxide is formed by dry oxidation with dichloroethylene.
Claim 5
Dependent Claim 15 words
The method of claim 1 wherein said nitrided oxide is annealed in an inert ambient.
Claim 6
Dependent Claim 15 words
The method of claim 1 wherein said nitrided oxide is annealed in a nitrogen ambient.
Claim 7
Dependent Claim 16 words
The method of claim 1 wherein said nitrided oxide is annealed with a rapid thermal process.
Claim 8
Dependent Claim 15 words
The method of claim 1 wherein said second oxide is formed by decomposing tetraethyl orthosilicate.
Claim 9
Independent Claim 120 words
A method of fabricating a field effect transistor comprising the steps of: forming a gate electrode over an insulating layer; forming a first oxide on the sidewalls of said gate electrode by dry oxidation; nitridating said first oxide in an ambient comprising ammonia with a rapid thermal process to create a nitrided oxide; annealing said nitrided oxide in a nitrogen ambient with a rapid thermal process to create an annealed nitrided oxide; forming a second oxide adjacent to said annealed nitrided oxide; forming a conformal layer comprising silicon nitride over said gate electrode and said annealed nitrided oxide; and anisotropically etching said conformal layer to create spacers for masking a lightly doped drain region from a high dose drain implant.
Claim 10
Independent Claim 120 words
A method of fabricating a field effect transistor comprising the steps of: forming a gate electrode over an insulating layer; forming a first oxide on the sidewalls of said gate electrode by dry oxidation; nitridating said first oxide in an ambient comprising ammonia with a rapid thermal process to create a nitrided oxide; annealing said nitrided oxide in a nitrogen ambient with a rapid thermal process to create an annealed nitrided oxide; forming a second oxide adjacent to said annealed nitrided oxide; forming a conformal layer comprising silicon nitride over said gate electrode and said annealed nitrided oxide; and anisotropically etching said conformal layer to create spacers for masking a lightly doped drain region from a high dose drain implant.
Claim 11
Dependent Claim 20 words
The method of claim 8 wherein said first oxide is nitridated at approximately 850 degrees Celsius for approximately thirty seconds.
Claim 12
Dependent Claim 19 words
The method of claim 8 wherein said nitrided oxide is annealed at approximately 1050 degrees for approximately sixty seconds.
Claim 13
Independent Claim 175 words
A method of fabricating a field effect transistor comprising the steps of: forming an insulating layer over a substrate of a first conductivity type; forming a gate electrode over said insulating layer; forming a first oxide on the sidewalls of said gate electrode by dry oxidation; nitridating said first oxide in an ambient comprising ammonia with a rapid thermal process to create a nitrided oxide; annealing said nitrided oxide in a nitrogen ambient with a rapid thermal process to create an annealed nitrided oxide; implanting a tip region with a first dose of dopant of a second conductivity type; forming a second oxide adjacent to said annealed nitrided oxide by decomposing tetraethyl orthosilicate; forming a conformal layer comprising silicon nitride over said gate electrode, said annealed nitrided oxide, and said second oxide; and anisotropically etching said conformal layer to create spacers for masking at least a portion of said tip region from a subsequent implant of a second dose of dopant of the second conductivity type, said second dose being greater than said first dose.
Claim 14
Independent Claim 175 words
A method of fabricating a field effect transistor comprising the steps of: forming an insulating layer over a substrate of a first conductivity type; forming a gate electrode over said insulating layer; forming a first oxide on the sidewalls of said gate electrode by dry oxidation; nitridating said first oxide in an ambient comprising ammonia with a rapid thermal process to create a nitrided oxide; annealing said nitrided oxide in a nitrogen ambient with a rapid thermal process to create an annealed nitrided oxide; implanting a tip region with a first dose of dopant of a second conductivity type; forming a second oxide adjacent to said annealed nitrided oxide by decomposing tetraethyl orthosilicate; forming a conformal layer comprising silicon nitride over said gate electrode, said annealed nitrided oxide, and said second oxide; and anisotropically etching said conformal layer to create spacers for masking at least a portion of said tip region from a subsequent implant of a second dose of dopant of the second conductivity type, said second dose being greater than said first dose.
Claim 15
Dependent Claim 45 words
The method of claim 11 wherein the step of implanting a tip region with a first dose of dopant of a second conductivity type is performed prior to the step of forming a first oxide on the sidewalls of said gate electrode by dry oxidation.
Claim 16
Dependent Claim 12 words
The method of claim 1 wherein said conformal layer comprises silicon nitride.

References Cited (Backward Citations)

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US5521127A Cited
US5436481A Cited
DE4337677A1 Cited
US5637528A Cited
US5620910A Cited
US5668036A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-10-26 2002-04-27 2002-10-27 $2000.00 Window Closed / Lapsed
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