Patent US5915190A successfully refreshed from Google Patents.
US5915190A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Methods for filling trenches in a semiconductor wafer
Assignee: Lam Research Corp
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Filing: 1997-07-30
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Granted: 1999-06-22
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Expires: 2017-07-30
Abstract
Abstract A method for filling a trench in a semiconductor wafer that is disposed in a plasma-enhanced chemical vapor deposition chamber. The method includes the step of depositing a protection layer of silicon dioxide over the wafer and into the trench while the wafer is biased at a first RF bias level. The protection layer has a thickness that is insufficient to completely fill the trench. Further, there is provided the step of forming a trench-fill layer of silicon dioxide over the protection layer and into the trench while the wafer is biased at a second RF bias level that is higher than the first bias level.
Inventors
- 👤 David R. Pirkle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:09
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/66; H10P14/668; H10P14/6681; H10P14/6682; H10P14/65; H10P14/6502; H10P14/6506; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/014; H10W10/10; H10W10/13; H10W10/17; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
174 words
In a plasma-enhanced chemical vapor deposition chamber, a method for filling a trench of a semiconductor device, comprising: depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench; and depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench-fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate, and wherein said second RF bias level causes sputtering, thereby causing said trench-fill material to be simultaneously sputtered and deposited over said protection layer and into said trench during said step of depositing said trench-fill layer.
Claim 2
Dependent Claim
174 words
In a plasma-enhanced chemical vapor deposition chamber, a method for filling a trench of a semiconductor device, comprising: depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench; and depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench-fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate, and wherein said second RF bias level causes sputtering, thereby causing said trench-fill material to be simultaneously sputtered and deposited over said protection layer and into said trench during said step of depositing said trench-fill layer.
Claim 3
Dependent Claim
31 words
The method of claim 1 wherein said protection layer is sufficiently thick so as to prevent damage to layers underneath said protection layer during said step of depositing said trench-fill layer.
Claim 4
Dependent Claim
27 words
The method of claim 1 wherein at least a portion of said wafer is covered with silicon nitride prior to said step of depositing said protection layer.
Claim 5
Dependent Claim
31 words
The method of claim 3 wherein said protection layer is sufficiently thick so as to prevent said silicon nitride layer from being damaged during said step of depositing said trench-fill layer.
Claim 6
Dependent Claim
22 words
The method of claim 1 further comprising the step of heating said wafer prior to said step of depositing said trench-fill layer.
Claim 7
Dependent Claim
35 words
The method of claim 5 wherein said heating step comprises the step of preheating said wafer radiantly in a chamber separate from said plasma processing chamber prior to said step of depositing said protection layer.
Claim 8
Dependent Claim
37 words
The method of claim 5 wherein said heating step comprises the step of preheating said wafer using convection heating in a chamber separate from said plasma processing chamber prior to said step of depositing said protection layer.
Claim 9
Independent Claim
176 words
A method for manufacturing an integrated circuit, comprising: providing a semiconductor wafer having a trench; filling said trench by: depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench, and depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate and wherein said second RF bias level causes sputtering, thereby causing said trench-fill material to be simultaneously sputtered and deposited over said protection layer and into said trench during said step of depositing said trench-fill layer.
Claim 10
Independent Claim
176 words
A method for manufacturing an integrated circuit, comprising: providing a semiconductor wafer having a trench; filling said trench by: depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench, and depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate and wherein said second RF bias level causes sputtering, thereby causing said trench-fill material to be simultaneously sputtered and deposited over said protection layer and into said trench during said step of depositing said trench-fill layer.
Claim 11
Dependent Claim
31 words
The method of claim 8 wherein said protection layer is sufficiently thick so as to prevent damage to layers underneath said protection layer during said step of depositing said trench-fill layer.
Claim 12
Dependent Claim
27 words
The method of claim 8 wherein at least a portion of said wafer is covered with silicon nitride prior to said step of depositing said protection layer.
Claim 13
Dependent Claim
31 words
The method of claim 10 wherein said protection layer is sufficiently thick so as to prevent said silicon nitride layer from being damaged during said step of depositing said trench-fill layer.
Claim 14
Dependent Claim
22 words
The method of claim 8 further comprising the step of heating said wafer prior to said step of depositing said trench-fill layer.
Claim 15
Dependent Claim
35 words
The method of claim 12 wherein said heating step comprises the step of preheating said wafer radiantly in a chamber separate from said plasma processing chamber prior to said step of depositing said protection layer.
Claim 16
Dependent Claim
37 words
The method of claim 12 wherein said heating step comprises the step of preheating said wafer using convection heating in a chamber separate from said plasma processing chamber prior to said step of depositing said protection layer.
Claim 17
Independent Claim
201 words
A method for manufacturing an integrated circuit, comprising: providing a semiconductor wafer having a trench; filling said trench by: depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench, and depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate and wherein a flow rate of a silicon-bearing source gas during said depositing said protection layer step is lower than a flow rate of said silicon-bearing source gas during said depositing said trench-fill layer step to compensate for a sputtering action during said depositing said trench-fill layer step, thereby improving a trench fill rate during said depositing said trench-fill layer step.
Claim 18
Independent Claim
201 words
A method for manufacturing an integrated circuit, comprising: providing a semiconductor wafer having a trench; filling said trench by: depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench, and depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate and wherein a flow rate of a silicon-bearing source gas during said depositing said protection layer step is lower than a flow rate of said silicon-bearing source gas during said depositing said trench-fill layer step to compensate for a sputtering action during said depositing said trench-fill layer step, thereby improving a trench fill rate during said depositing said trench-fill layer step.
Claim 19
Independent Claim
154 words
A method for manufacturing an integrated circuit, comprising: providing a semiconductor wafer having a trench; filling said trench by: depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench, and depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate and wherein said trench is employed to electrically isolate adjacent transistors from one another.
Claim 20
Independent Claim
154 words
A method for manufacturing an integrated circuit, comprising: providing a semiconductor wafer having a trench; filling said trench by: depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench, and depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate and wherein said trench is employed to electrically isolate adjacent transistors from one another.
Claim 21
Dependent Claim
197 words
In a plasma-enhanced chemical vapor deposition chamber, a method for filling a trench of a semiconductor device, comprising: depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench; and depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench-fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate, a flow rate of a silicon-bearing source gas during said depositing said protection layer step is lower than a flow rate of said silicon-bearing source gas during said depositing said trench-fill layer step to compensate for a sputtering action during said depositing said trench-fill layer step, thereby improving a trench fill rate during said depositing said trench-fill layer step.
Claim 22
Dependent Claim
197 words
In a plasma-enhanced chemical vapor deposition chamber, a method for filling a trench of a semiconductor device, comprising: depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench; and depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench-fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate, a flow rate of a silicon-bearing source gas during said depositing said protection layer step is lower than a flow rate of said silicon-bearing source gas during said depositing said trench-fill layer step to compensate for a sputtering action during said depositing said trench-fill layer step, thereby improving a trench fill rate during said depositing said trench-fill layer step.
Claim 23
Dependent Claim
150 words
In a plasma-enhanced chemical vapor deposition chamber, a method for filling a trench of a semiconductor device, comprising: depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench; and depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench-fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate, said trench is employed to electrically isolate adjacent transistors from one another.
Claim 24
Dependent Claim
150 words
In a plasma-enhanced chemical vapor deposition chamber, a method for filling a trench of a semiconductor device, comprising: depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench; and depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench-fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate, said trench is employed to electrically isolate adjacent transistors from one another.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-06-21 | 2002-12-21 | 2003-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-21 | 2006-12-21 | 2007-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-21 | 2010-12-21 | 2011-06-22 | $7700.00 | Window Closed / Lapsed |