US5498565A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming trench isolation having polishing step and method of manufacturing semiconductor device
Assignee: Sony Corp
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Filing: 1992-11-25
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Granted: 1996-03-12
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Expires: 2012-11-25
Abstract
Abstract A method of forming trench isolation including a burying step of burying trenches by a deposition means for conducting etching and deposition simultaneously and a polishing step of flattening a burying material by polishing is conducted by disposing an isotropic etching step, a multi-layered etching stopper and a protrusion unifying structure. Polishing can be attained with satisfactory flatness uniformly or with no polishing residue even in a portion to be polished in which the etching stopper layer is distributed unevenly. The method can be applied to manufacture of a semiconductor device or the like.
Inventors
- 👤 Tetsuo Gocho
- 👤 Hideaki Hayakawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:32
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/66; H10P14/668; H10P14/6681; H10P14/6684; H10P14/6686; H10P50/00; H10P50/20; H10P50/24; H10P50/242; H10P50/28; H10P50/282; H10P50/283; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/10; H10W10/17; H10P14/694; H10P14/6943; H10P14/69433; Y; Y10; Y10S; Y10S438/00; Y10S438/97
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
149 words
A method for manufacturing a semiconductor device having trench isolation structures in trenches in a substrate having wide and narrow protrusions between the trenches, comprising the steps of: burying the trenches by a deposition means by conducting etching and deposition of a burying material simultaneously on the substrate resulting in narrow build-up of burying material on the narrow protrusions and wide build-up of burying material on the wide protrusions; applying a resist on the substrate; forming a resist pattern in the resist to expose a surface of the burying material only on the wide protrusions while leaving the burying material on the narrow protrusions covered by the resist; after said step of forming, at least an isotropic etching step for isotropically etching through openings in the resist; and a polishing step for flattening the and any remaining portions of the the burying material on the wide protrusions by polishing.
Claim 2
Independent Claim
149 words
A method for manufacturing a semiconductor device having trench isolation structures in trenches in a substrate having wide and narrow protrusions between the trenches, comprising the steps of: burying the trenches by a deposition means by conducting etching and deposition of a burying material simultaneously on the substrate resulting in narrow build-up of burying material on the narrow protrusions and wide build-up of burying material on the wide protrusions; applying a resist on the substrate; forming a resist pattern in the resist to expose a surface of the burying material only on the wide protrusions while leaving the burying material on the narrow protrusions covered by the resist; after said step of forming, at least an isotropic etching step for isotropically etching through openings in the resist; and a polishing step for flattening the and any remaining portions of the the burying material on the wide protrusions by polishing.
Claim 3
Dependent Claim
140 words
A method of forming trench isolation structures as defined in claim 1, further comprising the steps of: applying an etching stopper to the substrate, the etching stopper comprising a three-layered structure, said step of applying an etching stopper including: applying an upper layer of said etching stopper layer of a film having a polishing rate slower than that of the burying material during the polishing step and an etching rate also slower than that of the burying material during the etching step, applying an intermediate layer of said etching stopper layer of a film having an etching rate slower than that of the upper layer during the etching step, and applying a lower layer of said etching stopper layer of a film having an etching rate slower than that of the intermediate layer and faster than that of the substrate.
References Cited (Backward Citations)
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WO1986002777A1
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JPS6484634A
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JPH02159050A
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JPH02294050A
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EP0407047A2
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JPH03139860A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-12 | 1999-09-11 | 2000-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-12 | 2003-09-11 | 2004-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-12 | 2007-09-11 | 2008-03-12 | $7700.00 | Window Closed / Lapsed |