Patent US5915167A successfully refreshed from Google Patents.
US5915167A
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Three dimensional structure memory
Assignee: ELM 3DS INNOVATONS LLC
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Filing: 1997-04-04
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Granted: 1999-06-22
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Expires: 2017-04-04
Abstract
Abstract A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
Inventors
- 👤 Glenn J. Leedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 23:55
CPC Classifications
H; H10; H10D; H10D84/00; B; B44; B44C; B44C1/00; B44C1/22; G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/84; G11C29/846; G11C5/00; G11C5/02; G11C5/025; G11C5/04; H10B; H10B12/00; H10B12/50; H10B99/00; H10D88/00; H10W; H10W20/00; H10W20/20; H10W70/00; H10W70/60; G11C29/04; G11C29/08; G11C29/12; G11C29/44; G11C29/80; G11C29/81; G11C29/848; H10W72/00; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/30; H10W72/351; H10W72/352; H10W90/00; H10W90/20; H10W90/297; Y; Y10; Y10S; Y10S438/00; Y10S438/977
Claims Analysis
Total Claims: 76
Claim 1
Independent Claim
116 words
A method of forming a random-access memory, comprising the steps of: fabricating a memory circuit on a first substrate; fabricating a memory controller circuit on a second substrate; bonding the first and second substrates to form interconnects between the memory circuit and the memory controller circuit, neither the first substrate alone nor the second substrate alone being sufficient to provide random access data storage, wherein said bonding is thermal diffusion bonding of the first substrate to the second substrate, and the backside of one of said substrates is thinned and then processed to form interconnection that pass through said one of said substrates and to form contacts on the backside of said one of said substrates.
Claim 2
Independent Claim
116 words
A method of forming a random-access memory, comprising the steps of: fabricating a memory circuit on a first substrate; fabricating a memory controller circuit on a second substrate; bonding the first and second substrates to form interconnects between the memory circuit and the memory controller circuit, neither the first substrate alone nor the second substrate alone being sufficient to provide random access data storage, wherein said bonding is thermal diffusion bonding of the first substrate to the second substrate, and the backside of one of said substrates is thinned and then processed to form interconnection that pass through said one of said substrates and to form contacts on the backside of said one of said substrates.
Claim 3
Dependent Claim
24 words
The method of claim 1, wherein at least some of said interconnects are fine-grain vertical interconnects having a pitch of less than 100 μm.
Claim 4
Dependent Claim
19 words
The method of claim 2, comprising the step of further bonding the stacked IC structure and a further substrate.
Claim 5
Dependent Claim
25 words
The method of claim 3, wherein said further bonding is thermal diffusion bonding of the stacked IC structure and the further substrate to one another.
Claim 6
Dependent Claim
23 words
The method of claim 4, wherein said thermal diffusion bonding uses fine-grain contact patterns having a contact pitch of less than 100 um.
Claim 7
Dependent Claim
17 words
The method of claim 5, wherein said fine-grain contact patterns form extensions of the fine-grain vertical interconnects.
Claim 8
Dependent Claim
19 words
The method of claim 1, comprising the step of further bonding the stacked IC structure and a further substrate.
Claim 9
Dependent Claim
22 words
The method of claim 7, wherein said further bonding is wire bonding of a singulated stacked IC structure and the further substrate.
Claim 10
Dependent Claim
18 words
The method of claim 1, wherein at least some of the interconnects arc formed by a planar process.
Claim 11
Dependent Claim
35 words
The method of claim 7, wherein said further bonding is thermal diffusion metal bonding of fine-grain vertical interconnect contact pattern of a singulated stacked IC structure and the further stacked IC or conventional circuit IC.
Claim 12
Dependent Claim
34 words
The method of claim 7, wherein said further bonding is thermal diffusion metal bonding of an interconnect contact pattern of a singulated stacked IC structure and the further stacked IC or conventional circuit IC.
Claim 13
Dependent Claim
18 words
The method of claim 10, wherein the first and second substrates are wire bonded to a third substrate.
Claim 14
Dependent Claim
70 words
The method of claim 1, comprising the further steps of: fabricating at least one additional memory circuit on at least one additional substrate; and bonding the at least one additional substrate to the stacked IC substrate and forming interconnects between the at least one additional memory circuit and the memory controller circuit, wherein at least some of the interconnects pass through a substrate on which a memory circuit is formed.
Claim 15
Dependent Claim
23 words
The method of claim 1, wherein said backside of said one of said substrates is thinned such that a thin device layer remains.
Claim 16
Dependent Claim
24 words
The method of claim 14, wherein at least some of said interconnects are fine-grain vertical interconnects having a pitch of less than 100 μm.
Claim 17
Dependent Claim
18 words
The method of claim 14, wherein said thinned substrates are thinned to less than 50 μm in thickness.
Claim 18
Dependent Claim
24 words
The method of claim 14, wherein semiconductor portions of the thinned substrates are thinned to a thickness in the range of about 1-8 μm.
Claim 19
Dependent Claim
12 words
The method of claim 14, wherein said thinning comprises grinding said substrates.
Claim 20
Dependent Claim
14 words
The method of claim 18, wherein said substrates are ground subsequent to being bonded.
Claim 21
Dependent Claim
14 words
The method of claim 18, wherein said substrates are ground prior to being bonded.
Claim 22
Dependent Claim
36 words
The method of claim 13, wherein at least one memory circuit is formed on a reusable substrate, further comprising the stop of separating a layer in which the memory circuit is formed from the reusable substrate.
Claim 23
Dependent Claim
17 words
The method of claim 21, wherein the at least one memory circuit is formed of polysilicon transistors.
Claim 24
Dependent Claim
18 words
The method of claim 13, wherein mating contact patterns are formed on respective surfaces to be bonded together.
Claim 25
Dependent Claim
15 words
The method of claim 23, wherein said mating contact patterns are formed predominantly of metal.
Claim 26
Dependent Claim
30 words
The method of claim 24, wherein said metal includes metal selected from a group consisting of: Al, Sn, Ti, In, Pb, Zn, Ni, Cu, Pt and Au, and alloys thereof.
Claim 27
Dependent Claim
44 words
The method of claim 13, wherein said memory circuits and said memory controller circuit are semiconductor circuits, and wherein the memory controller circuit is fabricated using a first semiconductor process technology and the memory circuits are formed using a second distinct semiconductor process technology.
Claim 28
Dependent Claim
25 words
The method of claim 26, wherein the first semiconductor process technology employs active semiconductor devices of both a first type and a second complementary type.
Claim 29
Dependent Claim
31 words
The method of claim 26, wherein semiconductor devices formed in accordance with the second semiconductor process technology include MOS semiconductor devices, the MOS semiconductor devices all being of a single type.
Claim 30
Independent Claim
97 words
A method of bonding together multiple substrates each having integrated circuits formed thereon to form interconnections between the integrated circuits, the method comprising the steps of: processing a mating surface on each of first and second substrates to achieve substantial planarity of the mating surfaces; forming mating, fine-grain interconnect patterns on the mating surfaces; performing fine-grain, planar thermal diffusion bonding of the mating surfaces; and thinning at least one of said substrates on which said integrated circuits are formed to form a thinned substrate, facilitating formation of said interconnects, and performing backside processing of said thinned substrate.
Claim 31
Independent Claim
97 words
A method of bonding together multiple substrates each having integrated circuits formed thereon to form interconnections between the integrated circuits, the method comprising the steps of: processing a mating surface on each of first and second substrates to achieve substantial planarity of the mating surfaces; forming mating, fine-grain interconnect patterns on the mating surfaces; performing fine-grain, planar thermal diffusion bonding of the mating surfaces; and thinning at least one of said substrates on which said integrated circuits are formed to form a thinned substrate, facilitating formation of said interconnects, and performing backside processing of said thinned substrate.
Claim 32
Dependent Claim
23 words
The method of claim 29, wherein said thermal diffusion bonding of the first substrate to the second substrate forms a stacked IC structure.
Claim 33
Dependent Claim
24 words
The method of claim 30, wherein at least some of said interconnects are fine-grain vertical interconnects having a pitch of less than 100 μm.
Claim 34
Dependent Claim
19 words
The method of claim 31, comprising the step of further bonding the stacked IC structure and a further substrate.
Claim 35
Dependent Claim
25 words
The method of claim 32, wherein said further bonding is thermal diffusion bonding of the stacked IC structure and the further substrate to one another.
Claim 36
Dependent Claim
23 words
The method of claim 33, wherein said thermal diffusion bonding uses fine-grain contact patterns having a contact pitch of less than 100 μm.
Claim 37
Dependent Claim
17 words
The method of claim 34, wherein said fine-grain contact patterns form extensions of the fine-grain vertical interconnects.
Claim 38
Dependent Claim
19 words
The method of claim 29, comprising the step of further bonding the stacked IC structure and a further substrate.
Claim 39
Dependent Claim
22 words
The method of claim 36, wherein said further bonding is wire bonding of a singulated stacked IC structure and the further substrate.
Claim 40
Dependent Claim
18 words
The method of claim 29, wherein at least some of the interconnects are formed by a planar process.
Claim 41
Dependent Claim
35 words
The method of claim 36, wherein said further bonding is thermal diffusion metal bonding of fine-grain vertical interconnect contact pattern of a singulated stacked IC structure and the further stacked IC or conventional circuit IC.
Claim 42
Dependent Claim
34 words
The method of claim 36, wherein said further bonding is thermal diffusion metal bonding of an interconnect contact pattern of a singulated stacked IC structure and the further stacked IC or conventional circuit IC.
Claim 43
Dependent Claim
18 words
The method of claim 39, wherein the first and second substrates are wire bonded to a third substrate.
Claim 44
Dependent Claim
23 words
The method of claim 29, wherein said backside of said one of said substrates is thinned such that a thin device layer remains.
Claim 45
Dependent Claim
24 words
The method of claim 42, wherein at least some of said interconnects are fine-grain vertical interconnects having a pitch of less than 100 μm.
Claim 46
Dependent Claim
18 words
The method of claim 42, wherein said thinned substrates are thinned to less than 50 μm in thickness.
Claim 47
Dependent Claim
24 words
The method of claim 42, wherein semiconductor portions of the thinned substrates are thinned to a thickness in the range of about 1-8 μm.
Claim 48
Dependent Claim
12 words
The method of claim 42, wherein said thinning comprises grinding said substrates.
Claim 49
Dependent Claim
14 words
The method of claim 46, wherein said substrates are ground subsequent to being bonded.
Claim 50
Dependent Claim
14 words
The method of claim 46, wherein said substrates are ground prior to being bonded.
Claim 51
Dependent Claim
36 words
The method of claim 41, wherein at least one integrated circuit is formed on a reusable substrate, further comprising the step of separating a layer in which the integrated circuit is formed from the reusable substrate.
Claim 52
Dependent Claim
17 words
The method of claim 49, wherein the at least one integrated circuit is formed of polysilicon transistors.
Claim 53
Dependent Claim
11 words
The method of claim 41, wherein bonding comprises thermal diffusion bonding.
Claim 54
Dependent Claim
18 words
The method of claim 51, wherein mating contact patterns are formed on respective surfaces to be bonded together.
Claim 55
Dependent Claim
15 words
The method of claim 52, wherein said mating contact patterns are formed predominantly of metal.
Claim 56
Dependent Claim
30 words
The method of claim 53, wherein said metal includes metal selected from a group consisting of: Al, Sn, Ti, In, Pb, Zn, Ni, Cu, Pt and Au, and alloys thereof.
Claim 57
Dependent Claim
29 words
The method of claim 1, comprising the further step of locating within the memory controller sense amplifiers, and coupling the sense amplifiers to data lines of the memory circuit.
Claim 58
Dependent Claim
32 words
The method of claim 55, comprising the further step of using the sense amplifiers to discriminate between more than two signal levels, and producing from each sense amplifier a multi-level output signal.
Claim 59
Dependent Claim
28 words
The method of claim 1, wherein said memory controller circuit is fabricated using a semiconductor process technology, and said memory circuits are formed using a different process technology.
Claim 60
Dependent Claim
27 words
The method of claim 57, wherein said different process technology is selected from a group consisting of: DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.
Claim 61
Dependent Claim
37 words
The method of claim 1, wherein surfaces bonded by thermal diffusion bonding include interconnect metallization and non-interconnect metallization; whereby thermal diffusion bonding simultaneously achieves electrical interconnection through said interconnect metallization and mechanical bonding through said non-interconnect metallization.
Claim 62
Dependent Claim
26 words
The method of claim 59 wherein, prior to said thermal diffusion bonding, at least one of the surfaces to be bonded is planarized using chemical/mechanical polishing.
Claim 63
Dependent Claim
18 words
The method of claim 60, wherein both of the surfaces to be bonded are planarized using chemical/mechanical polishing.
Claim 64
Dependent Claim
11 words
The method of claim 1, wherein said substrates are semiconductor wafers.
Claim 65
Dependent Claim
19 words
The method of claim 62 comprising the further step of dicing a resulting stacked wafer into individual stacked ICs.
Claim 66
Dependent Claim
19 words
The method of claim 1, wherein said memory controller circuit and said memory circuit are formed using low-stress dielectric.
Claim 67
Dependent Claim
34 words
The method of claim 13, comprising the further step of, during backside processing of a final substrate to form part of said random-access memory, forming bond pads on the backside of the final substrate.
Claim 68
Dependent Claim
37 words
The method of claim 29, wherein surfaces bonded by thermal diffusion bonding include interconnect metallization and non-interconnect metallization; whereby thermal diffusion bonding simultaneously achieves electrical interconnection through said interconnect metallization and mechanical bonding through said non-interconnect metallization.
Claim 69
Dependent Claim
26 words
The method of claim 29, wherein, prior to said thermal diffusion bonding, at least one of the surfaces to be bonded is planarized using chemical/mechanical polishing.
Claim 70
Dependent Claim
18 words
The method of claim 64, wherein both of the surfaces to be bonded are planarized using chemical/mechanical polishing.
Claim 71
Dependent Claim
11 words
The method of claim 29, wherein said substrates are semiconductor wafers.
Claim 72
Dependent Claim
19 words
The method of claim 69, comprising the further step of dicing a resulting stacked wafer into individual stacked ICs.
Claim 73
Dependent Claim
14 words
The method of claim 29, wherein said integrated circuits are formed using low-stress dielectric.
Claim 74
Dependent Claim
34 words
The method of claim 34, comprising the further step of, during backside processing of a final substrate to form part of said random-access memory, forming bond pads on the backside of the final substrate.
Claim 75
Independent Claim
84 words
A method of bonding together multiple substrates each having integrated circuits formed thereon to form interconnections between the integrated circuits, the method comprising the steps of: preparing on each of the first and second substrates substantially planar mating surfaces having mating contact patterns; performing thermal diffusion bonding of the mating surfaces; and thinning at least one of said substrates on which said integrated circuits are formed to form a thinned substrate, facilitating formation of said interconnects, and performing backside processing of said thinned substrate.
Claim 76
Independent Claim
84 words
A method of bonding together multiple substrates each having integrated circuits formed thereon to form interconnections between the integrated circuits, the method comprising the steps of: preparing on each of the first and second substrates substantially planar mating surfaces having mating contact patterns; performing thermal diffusion bonding of the mating surfaces; and thinning at least one of said substrates on which said integrated circuits are formed to form a thinned substrate, facilitating formation of said interconnects, and performing backside processing of said thinned substrate.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-06-21 | 2002-12-21 | 2003-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-21 | 2006-12-21 | 2007-06-22 | $3760.00 | Window Closed / Lapsed |
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