US5907462A
Expired / Lapsed
US
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Gate coupled SCR for ESD protection circuits
Assignee: Texas Instruments Inc
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Filing: 1994-09-07
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Granted: 1999-05-25
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Expires: 2014-09-07
Abstract
Abstract A protection device comprising a gate-coupled silicon-controlled rectifier (SCR) (100), SCR (100) comprises an anode (105) formed in n-well (104) and connected to a pad (128) and a cathode (111) connected to ground. A gate-coupled NMOS transistor (120) has a gate (116) connected through a resistive element (118) to ground. A n+ region (112) forms both the cathode (111) and a source of the NMOS transistor (120). N-well (104) forms the drain. Stress voltage is coupled from pad (128) to gate electrode (116) causing NMOS transistor (120) to conduct. This, in turn, triggers SCR (100) which dissipates the stress current at the pad (128). The coupled voltage at gate electrode (116) dissipates within a designed time constant through resistive element (118).
Inventors
- 👤 Amitava Chatterjee
- 👤 Charvaka Duvvury
- 👤 Ping Yang
- 👤 Ekanayake Ajith Amerasekera
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:14
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/711; H10D89/713; H10D8/00; H10D8/80
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
33 words
A protection device comprising a gate-coupled silicon-controlled rectifier (SCR) connected to a pad and incorporating a NMOS transistor, said NMOS transistor having a gate electrode electrically connected through a resistive element to ground.
Claim 2
Dependent Claim
33 words
A protection device comprising a gate-coupled silicon-controlled rectifier (SCR) connected to a pad and incorporating a NMOS transistor, said NMOS transistor having a gate electrode electrically connected through a resistive element to ground.
Claim 3
Dependent Claim
12 words
The device of claim 1, wherein said resistive element is a resistor.
Claim 4
Dependent Claim
22 words
The device of claim 1, wherein said resistive element is a second NMOS transistor having a gate connected to a supply voltage.
Claim 5
Dependent Claim
13 words
The device of claim 1, wherein said resistive element is a diode stack.
Claim 6
Dependent Claim
14 words
The device of claim 1, wherein said resistive element is greater than 10K ohms.
Claim 7
Dependent Claim
23 words
The device of claim 1, wherein said protection device has a trigger voltage greater than a supply voltage and less than 15 volts.
Claim 8
Dependent Claim
19 words
The device of claim 1, further comprising a discrete capacitor connected between said gate eletrode and an output pad.
Claim 9
Dependent Claim
20 words
The device of claim 7, wherein said discrete capacitor is a MOS transistor having its source and drain connected together.
Claim 10
Dependent Claim
52 words
The device of claim 1, further comprising a PMOS transistor having a source connected to said gate electrode a drain connected to said pad and a PMOS gate connected to a supply voltage, and a body node connected to said supply voltage to provide coupling between said gate electrode and the pad.
Claim 11
Dependent Claim
69 words
A protection device for protecting internal circuitry of an integrated circuit, comprising: a. a silicon-controlled rectifier (SCR) having an anode formed in a n-well and connected to a pad and a cathode formed in a substrate and connected to ground; and b. a gate-coupled NMOS transistor having a gate electrode tied through a resistive element to ground, wherein said cathode forms a source region of said gate-coupled NMOS transistor.
Claim 12
Dependent Claim
69 words
A protection device for protecting internal circuitry of an integrated circuit, comprising: a. a silicon-controlled rectifier (SCR) having an anode formed in a n-well and connected to a pad and a cathode formed in a substrate and connected to ground; and b. a gate-coupled NMOS transistor having a gate electrode tied through a resistive element to ground, wherein said cathode forms a source region of said gate-coupled NMOS transistor.
Claim 13
Dependent Claim
17 words
The device of claim 10, wherein said n-well forms a drain region of the gate-coupled NMOS transistor.
Claim 14
Dependent Claim
36 words
The device of claim 10, further comprising a n-type doped region at a surface of said substrate at an edge of said n-well, wherein said n-type doped region forms a drain of said gate-coupled NMOS transistor.
Claim 15
Dependent Claim
20 words
The protection device of claim 10, wherein said gate electrode extends over said n-well and onto a field oxide region.
Claim 16
Dependent Claim
59 words
The protection device of claim 10, wherein there is capacitive coupling, said capacitive coupling being the ratio of the gate-to-drain capacitance and the total gate capacitance to ground of the gate-coupled NMOS transistor and is selected such that a product of the capacitive coupling and a supply voltage is less than a threshold voltage of the gate-coupled NMOS transistor.
Claim 17
Dependent Claim
32 words
The protection device of claim 14, wherein a product of the capacitive coupling and a breakdown voltage of said internal circuitry is greater than the threshold voltage of the gate-coupled NMOS transistor.
Claim 18
Dependent Claim
31 words
The protection device of claim 10, further comprising a discrete capacitor connected between said pad and said gate electrode for coupling a stress voltage from said pad to said gate electrode.
Claim 19
Independent Claim
85 words
A method of protecting internal circuitry of an integrated circuit, comprising the steps of: a. coupling a stress voltage from a pad to a gate electrode of a NMOS transistor; b. conducting current in said NMOS transistor is response to said coupled stress voltage; c. triggering an SCR in response to said step of conducting current in said NMOS transistor to dissipate said stress voltage at said gate electrode; and d. dissipating said coupled stress voltage from said gate electrode through a resistor to ground.
Claim 20
Independent Claim
85 words
A method of protecting internal circuitry of an integrated circuit, comprising the steps of: a. coupling a stress voltage from a pad to a gate electrode of a NMOS transistor; b. conducting current in said NMOS transistor is response to said coupled stress voltage; c. triggering an SCR in response to said step of conducting current in said NMOS transistor to dissipate said stress voltage at said gate electrode; and d. dissipating said coupled stress voltage from said gate electrode through a resistor to ground.
Claim 21
Dependent Claim
25 words
The method of claim 17, wherein said step of dissipating said coupled stress voltage occurs in a time constant on the order of 10 nsec.
Claim 22
Dependent Claim
32 words
The method of claim 17, wherein said step of conducting current in said NMOS transistor occurs when said stress voltage at the pad reaches a selected voltage greater than a supply voltage.
Claim 23
Dependent Claim
87 words
An ESD protection circuit comprising: a lateral silicon-controlled rectifier (SCR) structure connected to a pad; a NMOS transistor located in the lateral SCR structure to lower a trigger voltage of said lateral SCR structure; a capacitor located between said pad and a gate of said NMOS transistor to couple an ESD-transient voltage to the gate of said NMOS transistor; and a resistance located between said gate of said NMOS transistor and ground to sustain the coupled ESD-transient voltage longer in time to effectively turn on the SCR.
Claim 24
Dependent Claim
87 words
An ESD protection circuit comprising: a lateral silicon-controlled rectifier (SCR) structure connected to a pad; a NMOS transistor located in the lateral SCR structure to lower a trigger voltage of said lateral SCR structure; a capacitor located between said pad and a gate of said NMOS transistor to couple an ESD-transient voltage to the gate of said NMOS transistor; and a resistance located between said gate of said NMOS transistor and ground to sustain the coupled ESD-transient voltage longer in time to effectively turn on the SCR.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-24 | 2002-11-23 | 2003-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-24 | 2006-11-23 | 2007-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-24 | 2010-11-23 | 2011-05-25 | $7700.00 | Window Closed / Lapsed |