US4739438A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit with an improved input protective device
Assignee: NEC Electronics Corp
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Filing: 1985-05-22
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Granted: 1988-04-19
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Expires: 2005-05-22
Abstract
Abstract The invention relates to an improved protective transistor arrangement for MIS circuits and the like which is capable of stable operation without breakdown in the event of a surge voltage. The protective transistor has a channel region whose length varies along the width of the channel such that the channel length at the central portion of the channel region is made less than the channel length at the sides of the channel region. By way of this construction, the current path through the protective transistor is largely confined to the central area of the channel region, preventing current from being concentrated at side portions of the channel region adjacent the field oxide surrounding the transistor.
Inventors
- 👤 Yoshinori Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:11
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811; H10D44/00; H10D44/40; H10D44/45
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
271 words
A semiconductor device, comprising; an external terminal, a functional transistor, first means for connecting said external terminal to said functional transistor, a protective transistor, second means for connecting one of a drain and source of said protective transistor to a part of an electrical path provided by said first means between said external terminal and said functional transistor, said protective transistor having an insulator layer including a contact hole for exposing only a center portion of a surface of said one of said drain and source thereof, said second means connecting said center portion to said electrical path formed by said first means, third means for connecting the other of said drain and source of said protective transistor to a predetermined voltage, and fourth means for biasing a gate of said protective transistor in such a manner that said protective transistor assumes a conductive state only when an excessive voltage outside of a normal operation voltage range is applied to said external terminal, said protective transistor being formed on a semiconductor substrate and surrounded by a field oxide formed on said substrate, both side portions of a channel region between source and drain regions of said protective transistor being adjacent said field oxide, the channel length at said side portions of said channel region of said protective transistor being longer than the channel length at a center portion of said channel region of said protective transistor, to thereby prevent a concentration of electric current at said side portions of said channel region when a current flows through said channel region upon the application of an excessive voltage to said external terminal.
Claim 2
Dependent Claim
271 words
A semiconductor device, comprising; an external terminal, a functional transistor, first means for connecting said external terminal to said functional transistor, a protective transistor, second means for connecting one of a drain and source of said protective transistor to a part of an electrical path provided by said first means between said external terminal and said functional transistor, said protective transistor having an insulator layer including a contact hole for exposing only a center portion of a surface of said one of said drain and source thereof, said second means connecting said center portion to said electrical path formed by said first means, third means for connecting the other of said drain and source of said protective transistor to a predetermined voltage, and fourth means for biasing a gate of said protective transistor in such a manner that said protective transistor assumes a conductive state only when an excessive voltage outside of a normal operation voltage range is applied to said external terminal, said protective transistor being formed on a semiconductor substrate and surrounded by a field oxide formed on said substrate, both side portions of a channel region between source and drain regions of said protective transistor being adjacent said field oxide, the channel length at said side portions of said channel region of said protective transistor being longer than the channel length at a center portion of said channel region of said protective transistor, to thereby prevent a concentration of electric current at said side portions of said channel region when a current flows through said channel region upon the application of an excessive voltage to said external terminal.
Claim 3
Dependent Claim
29 words
The semiconductor device according to claim 1, in which said fourth means includes a first resistive element coupled between the gate of said protecting transistor and said predetermined voltage.
Claim 4
Dependent Claim
26 words
The semiconductor device according to claim 1, in which said first means includes a second resistive element coupled between said functional transistor and said external terminal.
Claim 5
Dependent Claim
182 words
A semiconductor device, comprising; an input terminal, an input transistor, first means for electrically connecting a gate of said input transistor to said input terminal, a protective transistor formed on a semiconductor substrate, a length at a central portion of a channel region between source and drain regions of said protective transistor being shorter than a length at side portions of said channel region, one of said drain and source regions being covered by an insulating layer including a contact hole exposing only a central part of said one region, second means for electrically connecting said one of said drain and source of said protective transistor to the gate of said input transistor through said contact hole, third means for electrically connecting the other of said drain and source of said protective transistor to a reference voltage terminal, and a resistor coupled between the gate of said protective transistor and said reference voltage terminal whereby electric currents flowing through said protective transistor are concentrated at said central portion of said channel region when an excessive voltage is applied to said input terminal.
Claim 6
Dependent Claim
182 words
A semiconductor device, comprising; an input terminal, an input transistor, first means for electrically connecting a gate of said input transistor to said input terminal, a protective transistor formed on a semiconductor substrate, a length at a central portion of a channel region between source and drain regions of said protective transistor being shorter than a length at side portions of said channel region, one of said drain and source regions being covered by an insulating layer including a contact hole exposing only a central part of said one region, second means for electrically connecting said one of said drain and source of said protective transistor to the gate of said input transistor through said contact hole, third means for electrically connecting the other of said drain and source of said protective transistor to a reference voltage terminal, and a resistor coupled between the gate of said protective transistor and said reference voltage terminal whereby electric currents flowing through said protective transistor are concentrated at said central portion of said channel region when an excessive voltage is applied to said input terminal.
Claim 7
Dependent Claim
27 words
The device according to claim 4, in which said first means includes a resistive element coupled between said gate of said input transistor and said input terminal.
Claim 8
Dependent Claim
32 words
The device according to claim 4, in which said second means connects said one of drain and source of said protecting transistor to a part of electrical path of said first means.
Claim 9
Dependent Claim
235 words
A semiconductor device, comprising; an external terminal, a semiconductor substrate of a first conductivity type; a functional transistor formed on said substrate; a protective transistor formed on said substrate, said protective transistor having a channel region defined at a surface of said substrate, a gate formed on said channel region via an insulating layer, and first and second impurity regions of a second conductivity type spaced apart via said channel region, said first and second impurity regions serving as source and drain regions of said protective transistor, a channel length at side portions of said channel region being longer than a channel length at a center portion of said channel region; a field oxide selectively formed on the surface of said substrate and surrounding said functional and protective transistors; first means for connecting said external terminal to said functional transistor; second means for connecting said first impurity region to a part of an electrical path provided by said first means between said external terminal and said functional transistor, said second means including a layer covering said first impurity region and having a contact hole exposing a limited area of a central portion of said first impurity region for connection to said part of said electrical path; third means for connecting said second impurity region to a predetermined voltage source, and fourth means for connecting said gate of said protective transistor to said predetermined voltage source.
Claim 10
Dependent Claim
235 words
A semiconductor device, comprising; an external terminal, a semiconductor substrate of a first conductivity type; a functional transistor formed on said substrate; a protective transistor formed on said substrate, said protective transistor having a channel region defined at a surface of said substrate, a gate formed on said channel region via an insulating layer, and first and second impurity regions of a second conductivity type spaced apart via said channel region, said first and second impurity regions serving as source and drain regions of said protective transistor, a channel length at side portions of said channel region being longer than a channel length at a center portion of said channel region; a field oxide selectively formed on the surface of said substrate and surrounding said functional and protective transistors; first means for connecting said external terminal to said functional transistor; second means for connecting said first impurity region to a part of an electrical path provided by said first means between said external terminal and said functional transistor, said second means including a layer covering said first impurity region and having a contact hole exposing a limited area of a central portion of said first impurity region for connection to said part of said electrical path; third means for connecting said second impurity region to a predetermined voltage source, and fourth means for connecting said gate of said protective transistor to said predetermined voltage source.
Claim 11
Dependent Claim
30 words
The semiconductor device according to claim 7, in which said fourth means includes a first resistive element coupled between the gate of said protective transistor and said predetermined voltage source.
Claim 12
Dependent Claim
26 words
The semiconductor device according to claim 7, in which said first means includes a second resistive element coupled between said functional transistor and said external terminal.
Claim 13
Dependent Claim
194 words
A semiconductor device, comprising; an external terminal, a semiconductor substrate of a first conductivity type; a functional transistor formed on said substrate; a protective transistor formed on said substrate, said protective transistor having a channel region defined at a surface of said substrate, a gate formed on said channel region via an insulating layer, and first and second impurity regions of a second conductivity type spaced apart via said channel region, said first and second impurity regions serving as source and drain regions of said protective transistor, a channel length at side portions of said channel region being longer than a channel length at a center portion of said channel region; a third impurity region of said first conductivity type formed in said first impurity region; first means for connecting said external terminal to said functional transistor; second means for connecting said third impurity region to a part of an electrical path provided by said first means between said external terminal and said functional transistor; third means for connecting said second impurity region to a predetermined voltage source; and fourth means for connecting said gate of said protective transistor to said predetermined voltage source.
Claim 14
Dependent Claim
194 words
A semiconductor device, comprising; an external terminal, a semiconductor substrate of a first conductivity type; a functional transistor formed on said substrate; a protective transistor formed on said substrate, said protective transistor having a channel region defined at a surface of said substrate, a gate formed on said channel region via an insulating layer, and first and second impurity regions of a second conductivity type spaced apart via said channel region, said first and second impurity regions serving as source and drain regions of said protective transistor, a channel length at side portions of said channel region being longer than a channel length at a center portion of said channel region; a third impurity region of said first conductivity type formed in said first impurity region; first means for connecting said external terminal to said functional transistor; second means for connecting said third impurity region to a part of an electrical path provided by said first means between said external terminal and said functional transistor; third means for connecting said second impurity region to a predetermined voltage source; and fourth means for connecting said gate of said protective transistor to said predetermined voltage source.
Claim 15
Dependent Claim
25 words
The semiconductor device according to claim 10, in which said second means includes a resistive wiring having a part connected to said third impurity region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-19 | 1991-10-19 | 1992-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-19 | 1995-10-19 | 1996-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-19 | 1999-10-19 | 2000-04-19 | $7700.00 | Window Closed / Lapsed |