US3819952A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Mitsubishi Electric Corp
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Filing: 1973-01-29
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Granted: 1974-06-25
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Expires: 1993-01-29
Abstract
Abstract A first protecting insulated gate field effect (IGFE) transistor has a drain and a source connected respectively to a gate and a source of an IGFE transistor to be protected against overvoltages with the gate connected to an input through a resistor. A second protecting IGFE transistor higher in threshold voltage than the first protecting transistor has a source connected to the gate of the first protecting transistor and through another resistor to the source of the same transistor with its gate and drain operatively coupled to the input. The second protecting transistor first conducts in response to an overvoltage, applied to the input to decrease a voltage applied to the protected transistor and to conduct the first transistor. The conduction of the first transistor causes a voltage much decreased from the overvoltage to be applied to the protected transistor.
Inventors
- 👤 T Enomoto
- 👤 H Morita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 13:41
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/52; H03F1/523; H03K; H03K17/00; H03K17/08; H03K17/081; H03K17/0812; H03K17/08122
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
260 words
A semiconductor device, comprising: an insulated gate field effect transistor to be protected against overvoltages including a first gate electrode, a first source electrode and a first drain electrode; an input terminal; a resistor connected to said input terminal and to said first gate electrode of said protected, insulated gate field effect transistor; a first protecting insulated gate field effect transistor having a threshold voltage level and including a second drain electrode connected to said first gate electrode of said protected transistor a second source electrode connected to said first source electrode of said protected, insulated gate field effect transistor, and a second gate electrode; a second protecting, insulated gate field effect transistor having a second threshold voltage level higher than the threshold voltage level of said first protecting, insulated gate field effect transistor; and means for electrically connecting said second protecting insulated gate field effect transistor to both said input terminal and said first protecting, insulated gate field effect transistor, said second, protecting, insulated gate field effect transistor having a third source electrode connected to said second gate electrode of said first protecting, insulated field effect transistor and being responsive to a voltage applied to said input terminal in excess of the second threshold voltage level to thus conduct and provide an output voltage and said first protecting, insulated gate field effect transistor being responsive to said output voltage from said second protecting, insulated gate field effect transistor and being conductive, thus applying a reduced voltage to said first gate electrode of said protected, insulated gate field effect transistor.
Claim 2
Dependent Claim
260 words
A semiconductor device, comprising: an insulated gate field effect transistor to be protected against overvoltages including a first gate electrode, a first source electrode and a first drain electrode; an input terminal; a resistor connected to said input terminal and to said first gate electrode of said protected, insulated gate field effect transistor; a first protecting insulated gate field effect transistor having a threshold voltage level and including a second drain electrode connected to said first gate electrode of said protected transistor a second source electrode connected to said first source electrode of said protected, insulated gate field effect transistor, and a second gate electrode; a second protecting, insulated gate field effect transistor having a second threshold voltage level higher than the threshold voltage level of said first protecting, insulated gate field effect transistor; and means for electrically connecting said second protecting insulated gate field effect transistor to both said input terminal and said first protecting, insulated gate field effect transistor, said second, protecting, insulated gate field effect transistor having a third source electrode connected to said second gate electrode of said first protecting, insulated field effect transistor and being responsive to a voltage applied to said input terminal in excess of the second threshold voltage level to thus conduct and provide an output voltage and said first protecting, insulated gate field effect transistor being responsive to said output voltage from said second protecting, insulated gate field effect transistor and being conductive, thus applying a reduced voltage to said first gate electrode of said protected, insulated gate field effect transistor.
Claim 3
Dependent Claim
318 words
A semiconductor device, comprising in combination: an insulated gate field effect transistor to be protected against overvoltages including a first gate electrode, a first source electrode and a first drain electrode; an input terminal; a first protecting insulated gate field effect transistor having a first threshold voltage level and including a second drain electrode and a second source electrode respectively connected to said first gate and first source electrodes of said protected, insulated gate field effect transistor and further including a second gate electrode; a first resistor connected to said input terminal and to said second drain electrode of said first protecting, insulated gate field effect transistor; a second protecting, insulated gate field effect transistor including a third gate electrode connected to said input terminal, a third drain electrode connected to said second drain electrode of said first protecting, insulated gate field effect transistor and a third source electrode; a second resistor connected to said third source electrode of said second protecting insulated gate field effect transistor and to said first source electrode of said protected insulated gate field effect transistor, the junction of said second resistor and said third source electrode of said second protecting insulated gate field effect transistor being connected to said second gate electrode of said first protecting, insulated gate field effect transistor, said second protecting, insulated gate field effect transistor having a second threshold voltage higher than the first threshold vOltage of said first protecting, insulated gate field effect transistor and being responsive to a voltage applied to said input terminal in excess of the second threshold voltage and providing an output voltage, said first protecting, insulated gate field effect transistor being responsive to said output voltage from said second protecting, insulated gate field effect transistor exceeding the first threshold voltage to become conductive and thus apply a reduced voltage to said first gate electrode of said protected, insulated gate field effect transistor.
Claim 4
Dependent Claim
318 words
A semiconductor device, comprising in combination: an insulated gate field effect transistor to be protected against overvoltages including a first gate electrode, a first source electrode and a first drain electrode; an input terminal; a first protecting insulated gate field effect transistor having a first threshold voltage level and including a second drain electrode and a second source electrode respectively connected to said first gate and first source electrodes of said protected, insulated gate field effect transistor and further including a second gate electrode; a first resistor connected to said input terminal and to said second drain electrode of said first protecting, insulated gate field effect transistor; a second protecting, insulated gate field effect transistor including a third gate electrode connected to said input terminal, a third drain electrode connected to said second drain electrode of said first protecting, insulated gate field effect transistor and a third source electrode; a second resistor connected to said third source electrode of said second protecting insulated gate field effect transistor and to said first source electrode of said protected insulated gate field effect transistor, the junction of said second resistor and said third source electrode of said second protecting insulated gate field effect transistor being connected to said second gate electrode of said first protecting, insulated gate field effect transistor, said second protecting, insulated gate field effect transistor having a second threshold voltage higher than the first threshold vOltage of said first protecting, insulated gate field effect transistor and being responsive to a voltage applied to said input terminal in excess of the second threshold voltage and providing an output voltage, said first protecting, insulated gate field effect transistor being responsive to said output voltage from said second protecting, insulated gate field effect transistor exceeding the first threshold voltage to become conductive and thus apply a reduced voltage to said first gate electrode of said protected, insulated gate field effect transistor.
Claim 5
Dependent Claim
289 words
A semiconductor device, comprising in combination: an insulated gate field effect transistor to be protected against overvoltages including a first gate electrode, a first source electrode and a first drain electrode; an input terminal; a first protecting insulated gate field effect transistor having a first threshold level and including a second drain electrode and a second source electrode respectively connected to said first gate and first source electrodes of said protected, insulated gate field effect transistor and further including a second gate electrode; a first resistor connected between said input terminal and said second drain electrode of said first protecting, insulated gate field effect transistor; a second protecting, insulated gate field effect transistor including a third gate electrode and a third drain electrode connected together to said input terminal, and a third source electrode; and a second resistor connected between said third source electrode of said second protecting, insulated gate field effect transistor and said first source electrode of said protected, insulated gate field effect transistor, the junction of said second resistor and said third source electrode of said second protecting, insulated gate field effect transistor being connected to said first gate electrode of said first protecting, insulated gate field effect transistor said second protecting, insulated gate field effect transistor having a second threshold voltage level higher than the first threshold voltage level of said first protecting, insulated gate field effect transistor and being responsive to a voltage in excess of the second threshold voltage level applied to said input terminal to provide an output voltage to said first protecting, insulated gate field effect transistor exceeding the first threshold voltage and thus providing a reduced voltage to said first gate electrode of said protected, insulated gate field effect transistor.
Claim 6
Dependent Claim
289 words
A semiconductor device, comprising in combination: an insulated gate field effect transistor to be protected against overvoltages including a first gate electrode, a first source electrode and a first drain electrode; an input terminal; a first protecting insulated gate field effect transistor having a first threshold level and including a second drain electrode and a second source electrode respectively connected to said first gate and first source electrodes of said protected, insulated gate field effect transistor and further including a second gate electrode; a first resistor connected between said input terminal and said second drain electrode of said first protecting, insulated gate field effect transistor; a second protecting, insulated gate field effect transistor including a third gate electrode and a third drain electrode connected together to said input terminal, and a third source electrode; and a second resistor connected between said third source electrode of said second protecting, insulated gate field effect transistor and said first source electrode of said protected, insulated gate field effect transistor, the junction of said second resistor and said third source electrode of said second protecting, insulated gate field effect transistor being connected to said first gate electrode of said first protecting, insulated gate field effect transistor said second protecting, insulated gate field effect transistor having a second threshold voltage level higher than the first threshold voltage level of said first protecting, insulated gate field effect transistor and being responsive to a voltage in excess of the second threshold voltage level applied to said input terminal to provide an output voltage to said first protecting, insulated gate field effect transistor exceeding the first threshold voltage and thus providing a reduced voltage to said first gate electrode of said protected, insulated gate field effect transistor.
Claim 7
Dependent Claim
318 words
A semiconductor device, comprising in combination: an insulated gate field effect transistor to be protected against overvoltages including a first gate electrode a first source electrode and a first drain electrode; an input terminal; a first protecting insulated gate field effect transistor having a first threshold voltage level including a second drain electrode and a second source electrode connected to said first gate and first source electrode of said protected, insulated gate field effect transistor respectively and further including a second gate electrode; a first resistor connected between said input terminal and said second drain electrode of said first protecting, insulated gate field effect transistor; a second protecting, insulated gate field effect transistor including third gate electrode and a third drain electrode both connected to an electric path connecting said first resistor to said second drain electrode of said first protecting, insulated gate field effect transistor and further including a third source electrode; and a second resistor connected between said source electrode of said second protecting, insulated gate field effect transistor and said first source electrode of said protected, insulated gate field effect transistor, the junction of said second resistor and said third source electrode of said second protecting, insulated gate field effect transistor being connected to said second gate electrode of said first protecting, insulated gate field effect traNsistor, said second protecting, insulated gate field effect transistor having a second threshold voltage level higher than the first threshold voltage level of said first protecting insulated gate field effect transistor and being responsive to a voltage in excess of the second threshold voltage applied to said input terminal to provide an output voltage, said first protecting, insulated gate field effect transistor being responsive to said output voltage from said second protecting, insulated gate field effect transistor exceeding the first threshold voltage and providing a reduced voltage to said gate electrode of said protected, insulated gate field effect transistor.
Claim 8
Dependent Claim
318 words
A semiconductor device, comprising in combination: an insulated gate field effect transistor to be protected against overvoltages including a first gate electrode a first source electrode and a first drain electrode; an input terminal; a first protecting insulated gate field effect transistor having a first threshold voltage level including a second drain electrode and a second source electrode connected to said first gate and first source electrode of said protected, insulated gate field effect transistor respectively and further including a second gate electrode; a first resistor connected between said input terminal and said second drain electrode of said first protecting, insulated gate field effect transistor; a second protecting, insulated gate field effect transistor including third gate electrode and a third drain electrode both connected to an electric path connecting said first resistor to said second drain electrode of said first protecting, insulated gate field effect transistor and further including a third source electrode; and a second resistor connected between said source electrode of said second protecting, insulated gate field effect transistor and said first source electrode of said protected, insulated gate field effect transistor, the junction of said second resistor and said third source electrode of said second protecting, insulated gate field effect transistor being connected to said second gate electrode of said first protecting, insulated gate field effect traNsistor, said second protecting, insulated gate field effect transistor having a second threshold voltage level higher than the first threshold voltage level of said first protecting insulated gate field effect transistor and being responsive to a voltage in excess of the second threshold voltage applied to said input terminal to provide an output voltage, said first protecting, insulated gate field effect transistor being responsive to said output voltage from said second protecting, insulated gate field effect transistor exceeding the first threshold voltage and providing a reduced voltage to said gate electrode of said protected, insulated gate field effect transistor.
Claim 9
Dependent Claim
303 words
A semiconductor device, comprising in combination: an insulated gate field effect transistor to be protected against overvoltages including a first gate electrode, a first source electrode and a first drain electrode, an input terminal; a first protecting, insulated gate field effect transistor having a first threshold and a second source electrode connected respectively to said gate and source electrodes of said protected, insulated gate field effect transistor and further including a second gate electrode; a resistor connected between said input terminal and said first gate electrode of said protected, insulated gate field effect transistor; a second protecting, insulated gate field effect transistor including a third gate electrode and a third drain electrode both connected to an electric path connecting said input terminal to said second drain electrode of said first protecting insulated gate field effect transistor and further including a third source electrode connected to said second gate electrode of said first protecting, insulated gate field effect transistor, said second protecting, insulated gate field effect transistor having a second threshold voltage level higher than the first threshold voltage of said first protecting, insulated gate field effect transistor; and a third protecting, insulated gate field effect transistor including a fourth gate electrode connected to an electric source, a fourth drain electrode connected to said third source electrode of said second protecting, insulated gate field effect transistor being responsive to a voltage in excess of the second threshold voltage applied to said input terminal to provide an output voltage, and a fourth source electrode connected to said first source electrode, said first protecting, insulated gate field effect transistor being responsive to said output voltage from said second protecting, insulated gate field effect transistor exceeding the first threshold voltage to provide a reduced voltage to said gate electrode of said protected, insulated gate field effect transistor.
Claim 10
Dependent Claim
303 words
A semiconductor device, comprising in combination: an insulated gate field effect transistor to be protected against overvoltages including a first gate electrode, a first source electrode and a first drain electrode, an input terminal; a first protecting, insulated gate field effect transistor having a first threshold and a second source electrode connected respectively to said gate and source electrodes of said protected, insulated gate field effect transistor and further including a second gate electrode; a resistor connected between said input terminal and said first gate electrode of said protected, insulated gate field effect transistor; a second protecting, insulated gate field effect transistor including a third gate electrode and a third drain electrode both connected to an electric path connecting said input terminal to said second drain electrode of said first protecting insulated gate field effect transistor and further including a third source electrode connected to said second gate electrode of said first protecting, insulated gate field effect transistor, said second protecting, insulated gate field effect transistor having a second threshold voltage level higher than the first threshold voltage of said first protecting, insulated gate field effect transistor; and a third protecting, insulated gate field effect transistor including a fourth gate electrode connected to an electric source, a fourth drain electrode connected to said third source electrode of said second protecting, insulated gate field effect transistor being responsive to a voltage in excess of the second threshold voltage applied to said input terminal to provide an output voltage, and a fourth source electrode connected to said first source electrode, said first protecting, insulated gate field effect transistor being responsive to said output voltage from said second protecting, insulated gate field effect transistor exceeding the first threshold voltage to provide a reduced voltage to said gate electrode of said protected, insulated gate field effect transistor.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-24 | 1977-12-24 | 1978-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-24 | 1981-12-24 | 1982-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-24 | 1985-12-24 | 1986-06-25 | $7700.00 | Window Closed / Lapsed |