Semiconductor structure for protecting integrated circuit devices

Claim 2

In an semiconductor structure for protecting an integrated utilization circuit having a substrate, a bond pad, the utilization circuit including a signal terminal connected to the bond pad, a single semiconductor layer of a first conductivity type disposed on the substrate, the semiconductor layer having a surface, a first semiconductor region of a second conductivity type disposed in PN junction forming relation with the semiconductor layer, a second semiconductor region of the first conductivity type disposed in PN junction forming relation within the first semiconductor region; the improvement comprising: a third semiconductor region of the second conductivity type disposed in PN junction forming relation with the semiconductor layer; a fourth semiconductor region of the first conductivity type disposed in the semiconductor layer, the fourth semiconductor region being spaced adjacent to the first semiconductor region; a fifth semiconductor region of the same conductivity type as the semiconductor layer and positioned solely beneath the first and third semiconductor regions and disposed between the semiconductor layer and the substrate, the fifth semiconductor region having a lower resistivity than that of the semiconductor layer; first conductive means for connecting the bond pad to the third semiconductor region; a power supply terminal; and second conductive means for connecting the second semiconductor region to the fourth semiconductor region and to the power supply terminal.

Claim 3

A semiconductor structure according to claim 1 further comprising a sixth semiconductor region of the second conductivity type extending from the surface of the semiconductor layer to the substrate, the sixth semiconductor region surrounding the semiconductor layer.

Claim 4

A semiconductor structure according to claim 2 wherein the substrate material is silicon of P type conductivity.

Claim 5

A semiconductor protection circuit according to claim 3 wherein the layer is an epitaxial layer of N type conductivity.

Claim 6

The semiconductor structure of claim 4 further comprising: a linear operating resistive element as represented by the resistance of that portion of the semiconductor layer located between the fourth and the fifth semiconductor regions.

Claim 7

In a semiconductor structure for protecting an integrated utilization circuit having: a substrate, a bond pad, the utilization circuit including a single terminal connected to the bond pad a single semiconductor layer of a first conductivity type disposed on the substrate, the semiconductor layer having a surface, a first semiconductor region of a second conductivity type disposed in PN junction forming relation with the semiconductor layer, and a second semiconductor region of the first conductivity type disposed in PN junction forming relation within the first semiconductor region, the improvement comprising: a third semiconductor region of the second conductivity type in PN junction forming relation with the semiconductor layer; a fourth semiconductor region of the second conductivity type disposed in the semiconductor layer, the fourth semiconductor region being spaced adjacent to the first semiconductor region; a fifth semiconductor region of the first conductivity type extending from the surface of the semiconductor layer and being completely surrounded by the fourth semiconductor region; a sixth semiconductor region of the first conductivity type extending from the surface of the semiconductor layer adjacent to and abutting the fourth semiconductor region; a seventh semiconductor region of the same conductivity type as the semiconductor layer positioned solely beneath the first, third, fourth and sixth semiconductor regions and disposed between the semiconductor layer and the substrate, the seventh semiconductor region having a lower resistivity than that of the semiconductor layer; first conductive means for connecting the bond pad to the third semiconductor region; a power supply terminal; second conductive means for connecting the second semiconductor region to the fifth semiconductor region and to the power supply terminal; and third conductive means connecting the fourth semiconductor region to the sixth semiconductor region.

Claim 8

In a semiconductor structure for protecting an integrated utilization circuit having: a substrate, a bond pad, the utilization circuit including a single terminal connected to the bond pad a single semiconductor layer of a first conductivity type disposed on the substrate, the semiconductor layer having a surface, a first semiconductor region of a second conductivity type disposed in PN junction forming relation with the semiconductor layer, and a second semiconductor region of the first conductivity type disposed in PN junction forming relation within the first semiconductor region, the improvement comprising: a third semiconductor region of the second conductivity type in PN junction forming relation with the semiconductor layer; a fourth semiconductor region of the second conductivity type disposed in the semiconductor layer, the fourth semiconductor region being spaced adjacent to the first semiconductor region; a fifth semiconductor region of the first conductivity type extending from the surface of the semiconductor layer and being completely surrounded by the fourth semiconductor region; a sixth semiconductor region of the first conductivity type extending from the surface of the semiconductor layer adjacent to and abutting the fourth semiconductor region; a seventh semiconductor region of the same conductivity type as the semiconductor layer positioned solely beneath the first, third, fourth and sixth semiconductor regions and disposed between the semiconductor layer and the substrate, the seventh semiconductor region having a lower resistivity than that of the semiconductor layer; first conductive means for connecting the bond pad to the third semiconductor region; a power supply terminal; second conductive means for connecting the second semiconductor region to the fifth semiconductor region and to the power supply terminal; and third conductive means connecting the fourth semiconductor region to the sixth semiconductor region.

Claim 9

A semiconductor structure according to claim 6, is the comprising; an eighth semiconductor region, of the second conductivity type extending from the surface of the semiconductor layer to the substrate to surround the semiconductor layer.

Claim 10

A semiconductor structure according to claim 7, wherein the substrate material is silicon of P type conductivity.

Claim 11

A semiconductor structure according to claim 8, wherein the layer is an epitaxial layer of N type conductivity.

Claim 12

The semiconductor structure of claim 9, further comprising: a non-linear resistive element, as represented by a diode, formed at the junction of the fourth and fifth regions.