Electrostatic discharge suppression circuit employing low-voltage triggering silicon-controlled rectifier

Claim 2

A suppression circuit for dissipating an electrostatic discharge at an input and/or output node of an integrated circuit, said suppression circuit comprising: a silicon-controlled rectifier discharge circuit electrically coupled to the input and/or output node for dissipating the electrostatic discharge; and a trigger circuit electrically connected to the input and/or output node and to the discharge circuit, said trigger circuit providing low-voltage turn-on of said discharge circuit as the electrostatic discharge builds at the input and/or output node of the integrated circuit to thereby prevent damage to the integrated circuit due to said electrostatic discharge, said trigger circuit including a transistor having a control gate, the transistor further having a substrate coupled to a control electrode of the silicon-controlled rectifier discharge circuit, the trigger circuit further including a passive resistance capacitance (RC) circuit connected to the control gate and to the input and/or output node such that said control gate is electrically coupled to the input and/or output node across a capacitance and to ground across a resistance, the passive RC circuit inhibiting turn-on of the discharge circuit during normal integrated circuit operation.

Claim 3

The suppression circuit of claim 1, wherein said transistor comprises a field-effect transistor, said field-effect transistor being connected to turn on with occurrence of said electrostatic discharge at the input and/or output node of the integrated circuit, turn-on of said field-effect transistor providing turn-on of said silicon-controlled rectifier discharge circuit.

Claim 4

The suppression circuit of claim 1, wherein said integrated circuit comprises an integrated circuit chip.

Claim 5

A suppression circuit for dissipating an electrostatic discharge at an input and/or output node of an integrated circuit, said suppression circuit comprising: a discharge circuit electrically coupled to the input and/or output node for dissipating the electrostatic discharge, said discharge circuit including a first silicon-controlled rectifier and a second silicon-controlled rectifier, said first silicon-controlled rectifier being electrically coupled between the input and/or output node and a (Vdd) voltage supply node of the integrated circuit, and said second silicon-controlled rectifier being electrically coupled between the input and/or output node and a (Vss) voltage supply node of the integrated circuit; and a trigger circuit electrically connected to the input and/or output node and to the first silicon-controlled rectifier and the second silicon-controlled rectifier of the discharge circuit, said trigger circuit providing low-voltage turn-on of one of said first silicon-controlled rectifier and said second silicon-controlled rectifier in response to the electrostatic discharge occurring at the input and/or output node of the integrated circuit to thereby dissipate the electrostatic discharge and prevent damage to the integrated circuit, said trigger circuit including a first transistor and a second transistor, a substrate of said first transistor being coupled to a control electrode of the first silicon-controlled rectifier and a substrate of said second transistor being coupled to a control electrode of the second silicon-controlled rectifier, a control gate of said first transistor and a control gate of said second transistor each being electrically coupled to the input and/or output node across a capacitance and to ground across a resistance, the capacitance and resistance forming a passive circuit, whereby depending upon the polarity of said electrostatic discharge, either said first transistor or said second transistor turns-on with said electrostatic discharge to turn on the first silicon-controlled rectifier or the second silicon-controlled rectifier, respectively, the passive circuit inhibiting turn-on of the first and second transistors during normal integrated circuit operation.

Claim 6

A suppression circuit for dissipating an electrostatic discharge at an input and/or output node of an integrated circuit, said suppression circuit comprising: a discharge circuit electrically coupled to the input and/or output node for dissipating the electrostatic discharge, said discharge circuit including a first silicon-controlled rectifier and a second silicon-controlled rectifier, said first silicon-controlled rectifier being electrically coupled between the input and/or output node and a (Vdd) voltage supply node of the integrated circuit, and said second silicon-controlled rectifier being electrically coupled between the input and/or output node and a (Vss) voltage supply node of the integrated circuit; and a trigger circuit electrically connected to the input and/or output node and to the first silicon-controlled rectifier and the second silicon-controlled rectifier of the discharge circuit, said trigger circuit providing low-voltage turn-on of one of said first silicon-controlled rectifier and said second silicon-controlled rectifier in response to the electrostatic discharge occurring at the input and/or output node of the integrated circuit to thereby dissipate the electrostatic discharge and prevent damage to the integrated circuit, said trigger circuit including a first transistor and a second transistor, a substrate of said first transistor being coupled to a control electrode of the first silicon-controlled rectifier and a substrate of said second transistor being coupled to a control electrode of the second silicon-controlled rectifier, a control gate of said first transistor and a control gate of said second transistor each being electrically coupled to the input and/or output node across a capacitance and to ground across a resistance, the capacitance and resistance forming a passive circuit, whereby depending upon the polarity of said electrostatic discharge, either said first transistor or said second transistor turns-on with said electrostatic discharge to turn on the first silicon-controlled rectifier or the second silicon-controlled rectifier, respectively, the passive circuit inhibiting turn-on of the first and second transistors during normal integrated circuit operation.

Claim 7

The suppression circuit of claim 4, wherein said integrated circuit comprises an integrated circuit chip having multiple input and/or output nodes, and wherein said suppression circuit is electrically coupled to at least one of said multiple input and/or output nodes for suppression of an electrostatic discharge occurring thereat.

Claim 8

An integrated circuit chip comprising: an integrated circuit; multiple input and/or output pads coupled to the integrated circuit for external connection thereto; and multiple electrostatic discharge suppression circuits electrically coupled to said multiple input and/or output pads, each electrostatic discharge suppression circuit including a silicon-controlled rectifier discharge circuit for dissipating an electrostatic discharge at a respective input and/or output pad of said multiple input and/or output pads, and a trigger circuit electrically connected to said respective input and/or output pad and to said respective discharge circuit, said trigger circuit providing low-voltage turn-on of said respective discharge circuit with the electrostatic respective discharge at said input and/or output pad to thereby dissipate the electrostatic discharge and prevent damage to the integrated circuit, said trigger circuit including a transistor having a control gate, the transistor further having a substrate coupled to a control electrode of the silicon-controlled rectifier discharge circuit, the trigger circuit further including a passive resistance capacitance (RC) circuit connected to the control gate and to said respective input and/or output pad such that said control gate is electrically coupled to the respective input and/or output pad across a capacitance and to ground across a resistance, the passive RC circuit inhibiting turn-on of the respective discharge circuit during normal integrated circuit operation.

Claim 9

An integrated circuit chip comprising: an integrated circuit; multiple input and/or output pads coupled to the integrated circuit for external connection thereto; and multiple electrostatic discharge suppression circuits electrically coupled to said multiple input and/or output pads, each electrostatic discharge suppression circuit including a silicon-controlled rectifier discharge circuit for dissipating an electrostatic discharge at a respective input and/or output pad of said multiple input and/or output pads, and a trigger circuit electrically connected to said respective input and/or output pad and to said respective discharge circuit, said trigger circuit providing low-voltage turn-on of said respective discharge circuit with the electrostatic respective discharge at said input and/or output pad to thereby dissipate the electrostatic discharge and prevent damage to the integrated circuit, said trigger circuit including a transistor having a control gate, the transistor further having a substrate coupled to a control electrode of the silicon-controlled rectifier discharge circuit, the trigger circuit further including a passive resistance capacitance (RC) circuit connected to the control gate and to said respective input and/or output pad such that said control gate is electrically coupled to the respective input and/or output pad across a capacitance and to ground across a resistance, the passive RC circuit inhibiting turn-on of the respective discharge circuit during normal integrated circuit operation.