US5289334A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS on-chip ESD protection circuit and semiconductor structure
Assignee: United Microelectronics Corp
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Filing: 1992-11-18
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Granted: 1994-02-22
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Expires: 2012-11-18
Abstract
Abstract A circuit for protecting a CMOS chip against damage from electrostatic discharges (ESD) has four SCRs connected between the line to be protected and the two power supply terminals, V DD and V SS . The SCRs are poled to conduct ESD current of either polarity to each power supply terminal. The bipolar transistors for the SCRs and the associated components are arranged in the chip in an advantageous way that reduces the input/output parasitic capacitance and improves the protection capability of this proposed circuit with a low ESD trigger-on voltage.
Inventors
- 👤 Ming-Dou Ker
- 👤 Chung-Yuan Lee
- 👤 Chung-Yu Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:02
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/711; H10D89/713; H02; H02H; H02H9/00; H02H9/04; H02H9/045; H02H9/046
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
167 words
A protection circuit for protecting an I/O pad and associated components on a CMOS chip from an excessive ESD voltage, where the chip has a negative power supply terminal (V SS ) and a positive power supply terminal (V DD ), wherein the improvement comprises, a first SCR circuit connected to conduct ESD currents of one polarity between the positive power supply terminal and the I/O pad, a second SCR circuit connected to conduct ESD currents of the other polarity between the positive power supply terminal and the I/O pad, a third SCR circuit connected to conduct ESD currents of said one polarity between the negative power supply terminal and the I/O pad, and a fourth SCR circuit connected to conduct ESD currents of said other polarity between the negative power supply terminal and the I/O pad, whereby the protection circuit operates for each polarity of ESD current in response to the magnitude of the ESD voltage with respect to the voltage of the power supply terminals.
Claim 2
Dependent Claim
167 words
A protection circuit for protecting an I/O pad and associated components on a CMOS chip from an excessive ESD voltage, where the chip has a negative power supply terminal (V SS ) and a positive power supply terminal (V DD ), wherein the improvement comprises, a first SCR circuit connected to conduct ESD currents of one polarity between the positive power supply terminal and the I/O pad, a second SCR circuit connected to conduct ESD currents of the other polarity between the positive power supply terminal and the I/O pad, a third SCR circuit connected to conduct ESD currents of said one polarity between the negative power supply terminal and the I/O pad, and a fourth SCR circuit connected to conduct ESD currents of said other polarity between the negative power supply terminal and the I/O pad, whereby the protection circuit operates for each polarity of ESD current in response to the magnitude of the ESD voltage with respect to the voltage of the power supply terminals.
Claim 3
Dependent Claim
26 words
The protection circuit of claim 1 wherein SCRs are formed with a small spacing between the anode and the cathode for providing a low turn-on voltage.
Claim 4
Dependent Claim
20 words
The protection circuit of claim 2 wherein the SCRs each comprise a vertical bipolar transistor and a lateral bipolar transistor.
References Cited (Backward Citations)
US4484244A
Cited
US4855620A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-21 | 1997-08-23 | 1998-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-21 | 2001-08-23 | 2002-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-21 | 2005-08-23 | 2006-02-22 | $7700.00 | Window Closed / Lapsed |