Ferroelectric memory using ferroelectric reference cells

Claim 2

An integrated memory circuit comprising: an array of ferroelectric memory cells; a multiplexed sense amplifier coupled to the array for sensing and amplifying data stored on the ferroelectric memory cells; a first and a second reference circuit coupled to the array for providing a reference voltage that is compared to a voltage representative of data stored on the ferroelectric memory cells using the multiplexed sense amplifier; and an alternate reference voltage circuit coupled to the first reference circuit providing a reference voltage which is substantially stable over time.

Claim 3

The integrated memory circuit of claim 1 wherein the reference voltage circuit is comprised of a non-remnant capacitor circuit.

Claim 4

The integrated memory circuit of claim 2 wherein the non-remnant capacitor circuit is coupled to a voltage regulator.

Claim 5

The integrated memory circuit of claim 2 wherein the non-remnant capacitor circuit is comprised of a conductor line having a line capacitance and one or more capacitors selectively coupled to the conductor line via access devices.

Claim 6

The integrated memory circuit of claim 4 wherein a capacitance of the non-remnant capacitor circuit is substantially lower than a bit line capacitance.

Claim 7

The integrated memory circuit of claim 1 wherein the array is arranged in addressable rows and columns and a ferroelectric memory cell is located at the intersection of each row and column, and each ferroelectric memory cell comprises a single ferroelectric capacitor.

Claim 8

The integrated memory circuit of claim 6 wherein the array of ferroelectric memory cells utilizes a folded bit line architecture in which bit lines for adjacent columns have staggered cells such that a word line from a row does not activate ferroelectric memory cells on adjacent bit lines.

Claim 9

The integrated memory circuit of claim 1 wherein the multiplexed sense amplifier uses a single ended reference voltage from either the first reference circuit, the second reference circuit, or the alternate reference voltage circuit.

Claim 10

The integrated memory circuit of claim 1 wherein the first and second reference circuits are comprised of a plurality of ferroelectric reference cells.

Claim 11

The integrated memory circuit of claim 9 wherein the plurality of ferroelectric reference cells are an even number, and a first one-half of the plurality of ferroelectric reference cells are polarized in one logical state and a second one-half of the plurality of ferroelectric reference cells are polarized in an opposite logical state.

Claim 12

The integrated memory circuit of claim 9 wherein the content of a ferroelectric memory cell being read and the ferroelectric reference cells can be rewritten on a same clock cycle.

Claim 13

An integrated memory circuit comprising: an array of ferroelectric memory cells; a multiplexed sense amplifier coupled to the array for sensing and amplifying data stored on the ferroelectric memory cells; a first reference circuit coupled to the array and having two ferroelectric reference cells, wherein the first reference circuit provides a reference voltage that is compared to a voltage representative of data stored on the memory cells using the multiplexed sense amplifier; a second reference circuit coupled to the array and having two ferroelectric reference cells, wherein the second reference circuit provides a reference voltage that is compared to a voltage representative of data stored on the memory cells using the multiplexed sense amplifier; and an alternate reference voltage circuit coupled to the first reference circuit providing a reference voltage which is substantially stable over time.

Claim 14

An integrated memory circuit comprising: an array of ferroelectric memory cells; a multiplexed sense amplifier coupled to the array for sensing and amplifying data stored on the ferroelectric memory cells; a first reference circuit coupled to the array and having two ferroelectric reference cells, wherein the first reference circuit provides a reference voltage that is compared to a voltage representative of data stored on the memory cells using the multiplexed sense amplifier; a second reference circuit coupled to the array and having two ferroelectric reference cells, wherein the second reference circuit provides a reference voltage that is compared to a voltage representative of data stored on the memory cells using the multiplexed sense amplifier; and an alternate reference voltage circuit coupled to the first reference circuit providing a reference voltage which is substantially stable over time.

Claim 15

The integrated memory circuit of claim 12 wherein the reference voltage circuit is comprised of a non-remnant capacitor circuit coupled to a voltage regulator.

Claim 16

The computer system of claim 12 wherein one-half of the ferroelectric reference cells are polarized in one logical state and a second one-half of the ferroelectric reference cells are polarized in an opposite logical state.

Claim 17

The computer system of claim 12 wherein the array of ferroelectric memory cells utilizes a folded bit line architecture in which bit lines for adjacent columns have staggered cells such that a word line from a row does not activate ferroelectric memory cells on adjacent bit lines.

Claim 18

The computer system of claim 12 wherein the multiplexed sense amplifier uses a single ended reference voltage from either the first reference circuit, the second reference circuit, or the alternate reference voltage circuit.

Claim 19

A computer system comprising: a processor; and a memory device coupled to the processor, wherein the processor defines memory access cycles, the memory device comprising: a memory array of ferroelectric memory cells; a plurality of paired digit line sections coupled to the memory array; a multiplexed sense amplifier connected between first and second digit lines of a first one and second one of the plurality of paired digit line sections for sensing and amplifying data stored on the ferroelectric memory cells; a first reference circuit connected between first and second digit lines of the first one of the plurality of paired digit line sections for providing a reference voltage that is compared to a voltage representative of data stored on the ferroelectric memory cells using the multiplexed sense amplifier; a second reference circuit connected between first and second digit lines of the second one of the plurality of paired digit line sections for providing a reference voltage that is compared to a voltage representative of data stored on the ferroelectric memory cells using the multiplexed sense amplifier; and an alternate reference voltage circuit coupled to the first reference circuit providing a reference voltage which is substantially stable over time.

Claim 20

A computer system comprising: a processor; and a memory device coupled to the processor, wherein the processor defines memory access cycles, the memory device comprising: a memory array of ferroelectric memory cells; a plurality of paired digit line sections coupled to the memory array; a multiplexed sense amplifier connected between first and second digit lines of a first one and second one of the plurality of paired digit line sections for sensing and amplifying data stored on the ferroelectric memory cells; a first reference circuit connected between first and second digit lines of the first one of the plurality of paired digit line sections for providing a reference voltage that is compared to a voltage representative of data stored on the ferroelectric memory cells using the multiplexed sense amplifier; a second reference circuit connected between first and second digit lines of the second one of the plurality of paired digit line sections for providing a reference voltage that is compared to a voltage representative of data stored on the ferroelectric memory cells using the multiplexed sense amplifier; and an alternate reference voltage circuit coupled to the first reference circuit providing a reference voltage which is substantially stable over time.

Claim 21

The computer system of claim 17 wherein the array of ferroelectric memory cells utilizes a folded bit line architecture in which bit lines for adjacent columns have staggered cells such that a word line from a row does not activate ferroelectric memory cells on adjacent bit lines.