Ultra-short transistor fabrication scheme for enhanced reliability

Abstract

Abstract A detached drain transistor including a semiconductor substrate, a gate dielectric formed on an upper surface of the substrate, a conductive gate formed on the gate dielectric, a first pair of spacer structures, a first source impurity distribution, a second pair of spacer structures, and a drain impurity distribution. The conductive gate is laterally disposed over a channel region of the semiconductor substrate. The channel region extends laterally between a first source region of the semiconductor substrate and a detached drain region of the semiconductor substrate. A channel boundary of the detached region is laterally displaced from a first sidewall of the conductive gate by a drain displacement. A channel boundary of the first source region is laterally displaced from a second sidewall of the conductive gate by a source displacement. The first pair of spacer structures is formed in contact with the first and second sidewalls of the conductive gate. A lateral dimension of the first pair of spacer structures is approximately equal to the source displacement. The second pair of spacer structures is formed on exterior sidewalls of the first pair of spacer structures such that exterior sidewalls of the second pair of spacer structures are displaced from respective sidewalls of the conductive gate by approximately said drain displacement. In a presently preferred embodiment, the source displacement is approximately 50 to 400 angstroms while the drain displacement is approximately 500 to 1500 angstroms.

Inventors

• 👤 Mark I. Gardner
• 👤 H. Jim Fulford, Jr.

Bibliographic Details