US5583067A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Inverse T-gate semiconductor device with self-aligned punchthrough stops and method of fabrication
Assignee: Intel Corp
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Filing: 1996-02-16
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Granted: 1996-12-10
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Expires: 2016-02-16
Abstract
Abstract A high speed submicron metal-oxide-semiconductor transistor which exhibits a high immunity to hot electron degradation, good performance, and excellent punchthrough characteristics. An inverse T gate comprising an upper member and a lower member is formed on a well of a first conductivity type. A gate insulating layer is formed between the composite gate and the well. A pair of first conductivity type punchthrough stop regions are formed apart in the well in alignment with the laterally opposite sides of the upper gate member. A first oxide sidewall spacer is formed adjacent to laterally opposite sidewalls of the upper gate member on the lower gate member. A first pair of source/drain regions of a second conductivity type are formed in alignment with the first oxide sidewall spacers. A second sidewall spacer is formed adjacent to each of the first sidewall spacers on the lower gate member. A second source and second drain region of the second conductivity type are formed in the first source and first drain regions, respectively. The second source and second drain regions are formed in alignment with the outer edges of the second sidewall spacers.
Inventors
- 👤 Julian J. Sanchez
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:27
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0212; H10D30/0227; H10D30/60; H10D30/601; H10D30/605; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01316; H10D64/01324; H10D64/021; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/665
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
183 words
A process for making a metal-oxide-semiconductor transistor on a well of a first concentration of a first conductivity type comprising the steps of: forming a gate insulating layer on said well; forming a first conductive layer on said insulating layer; forming a second conductive layer on said first conductive layer; forming an upper gate member of a first length from said second conductive layer, said upper gate member including laterally opposite sidewalls along the width of said upper gate member; implanting ions of said first conductivity type through said first conductive layer into said well in alignment with said laterally opposite sidewalls of said upper gate member to form a first and a second punchthrough stop region; forming a first sidewall spacer on opposite sides of said upper gate member on said first conductive layer; and forming a first source region and a first drain region of a first concentration of a second conductivity type in said first and second punchthrough stop regions, respectively, said first source and first drain regions formed in alignment with the outer edges of said first sidewall spacers.
Claim 2
Dependent Claim
183 words
A process for making a metal-oxide-semiconductor transistor on a well of a first concentration of a first conductivity type comprising the steps of: forming a gate insulating layer on said well; forming a first conductive layer on said insulating layer; forming a second conductive layer on said first conductive layer; forming an upper gate member of a first length from said second conductive layer, said upper gate member including laterally opposite sidewalls along the width of said upper gate member; implanting ions of said first conductivity type through said first conductive layer into said well in alignment with said laterally opposite sidewalls of said upper gate member to form a first and a second punchthrough stop region; forming a first sidewall spacer on opposite sides of said upper gate member on said first conductive layer; and forming a first source region and a first drain region of a first concentration of a second conductivity type in said first and second punchthrough stop regions, respectively, said first source and first drain regions formed in alignment with the outer edges of said first sidewall spacers.
Claim 3
Dependent Claim
72 words
The process for making a metal oxide semiconductor transistor of claim 1 further comprising the steps of: forming a second sidewall spacer adjacent to each of said first sidewall spacers on said first conductive layer; and forming a second source and a second drain region of a second concentration of said second conductivity type, said second source and second drain regions formed in said first source and said first drain regions, respectively.
Claim 4
Dependent Claim
26 words
The process of claim 2 further comprising the step of forming silicide on said upper gate member and on said second source and second drain regions.
Claim 5
Dependent Claim
21 words
The process of claim 1 wherein said first conductivity type is P-type conductivity and said second conductivity is N type conductivity.
Claim 6
Dependent Claim
12 words
The process of claim 1 wherein said first conductive layer is tungsten.
Claim 7
Dependent Claim
12 words
The process of claim 1 wherein said second conductive layer is polysilicon.
Claim 8
Dependent Claim
12 words
The process of claim 5 wherein said second conductive layer is polysilicon.
Claim 9
Dependent Claim
12 words
The process of claim 1 wherein said first conductive layer is polysilicon.
Claim 10
Dependent Claim
12 words
The process of claim 8 wherein said second conductive layer is tungsten.
Claim 11
Dependent Claim
12 words
The process of claim 8 wherein said second conductive layer is polysilicon.
Claim 12
Dependent Claim
26 words
The process of claim 1 further comprising a step of making a threshold implant of first conductivity type ions into the upper surface of said well.
Claim 13
Independent Claim
162 words
A method of forming a transistor on a substrate region of a first concentration of a first conductivity type, the method comprising the steps of: forming a gate insulating layer on said substrate region; forming a first conductive layer on said gate insulating layer; forming a second conductive layer on said first conductive layer; forming an upper gate member of a first length from said second conductive layer, said upper gate member including laterally opposite sidewalls along the width of said upper gate member; implanting ions of said first conductivity type through said first conductive layer into said substrate in alignment with said laterally opposite sidewalls of said upper gate member to form a punchthrough stop region; forming a first sidewall spacer on opposite sides of said upper gate member; and implanting ions into said substrate in alignment with said first sidewall spacer to form a first source and a first drain region of a first concentration of a second conductivity type.
Claim 14
Independent Claim
162 words
A method of forming a transistor on a substrate region of a first concentration of a first conductivity type, the method comprising the steps of: forming a gate insulating layer on said substrate region; forming a first conductive layer on said gate insulating layer; forming a second conductive layer on said first conductive layer; forming an upper gate member of a first length from said second conductive layer, said upper gate member including laterally opposite sidewalls along the width of said upper gate member; implanting ions of said first conductivity type through said first conductive layer into said substrate in alignment with said laterally opposite sidewalls of said upper gate member to form a punchthrough stop region; forming a first sidewall spacer on opposite sides of said upper gate member; and implanting ions into said substrate in alignment with said first sidewall spacer to form a first source and a first drain region of a first concentration of a second conductivity type.
Claim 15
Dependent Claim
42 words
The method of claim 12 further comprising the steps of: forming a second sidewall spacer adjacent of each of said first sidewall spacers; and forming a second source and a second drain region of a second concentration of said second conductivity type.
Claim 16
Dependent Claim
30 words
The method of claim 12 further comprising a step of implanting ions of said first conductivity type ion into the upper surface of said substrate to form a threshold implant.
Claim 17
Dependent Claim
26 words
The process of claim 13 further comprising the step of forming silicide on the upper gate member and on said second source and second drain regions.
Claim 18
Dependent Claim
12 words
The method of claim 12 wherein said upper gate member comprises polysilicon.
Claim 19
Dependent Claim
12 words
The method of claim 12 wherein said bottom gate member comprises tungsten.
References Cited (Backward Citations)
US5028552A
Cited
US4949136A
Cited
US5183771A
Cited
US4984042A
Cited
US5296401A
Cited
US5091763A
Cited
US5097301A
Cited
US5219777A
Cited
US5320974A
Cited
US5182619A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-10 | 2000-06-10 | 2000-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-10 | 2004-06-10 | 2004-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-10 | 2008-06-10 | 2008-12-10 | $7700.00 | Window Closed / Lapsed |