Method of manufacture of pull down transistor with drain off-set for low leakage SRAM's

Claim 1

A process of forming an asymmetric pull-down transistor within an SRAM, the process comprising a) forming a polysilicon gate structure on a semiconductor substrate of a first conductivity type; b) forming a mask in an area on the drain side of said polysilicon gate structure, leaving the remainder of said gate structure as well as a portion of said substrate unmasked, c) implanting a first N-type dopant into the unmasked areas of said substrate to form source and drain regions with an N+ doped region of said drain offset away from said gate structure by said mask and with an N+ doped region of said source aligned to the edge of said gate structure, d) forming insulating spacers proximate said gate structure, e) implanting a second dopant into the outer portion of said source region beyond said spacer and below said source region beyond said spacer and into and extending below said N+ doped region of said drain and between said N+ doped region of said drain and said spacer proximate thereto said second dopant being an N- dopant, thereby forming a pull down transistor coupled to other devices within an SRAM, whereby said SRAM is a low leakage SRAM device.