Thin film semiconductor device with gate metal oxide and sidewall spacer

Claim 2

A semiconductor device comprising: a substrate having an insulting surface; and a plurality of thin film transistors formed on said insulating surface, at least one of said thin film transistors comprising a silicon semiconductor layer including source, drain and channel regions, metal silicide regions connected to said source and drain regions, a gate insulating layer formed on said semiconductor layer, a gate electrode formed on said gate insulating layer, and an oxide insulating layer comprising an oxide of a material of said gate electrode formed on at least side surfaces of said gate electrode, wherein said at least one of the thin film transistors is provided with side spacers adjacent to the side surfaces of said gate electrode with said oxide insulating layer interposed therebetween, and inner edges of said metal silicide regions are substantially aligned with outer edges of said side spacers.

Claim 3

The semiconductor device of claim 1 wherein said metal is selected from the group consisting of molybdenum (Mo), tungsten (W), platinum (Pt), chromium (Cr), titanium (Ti), and cobalt (Co).

Claim 4

The semiconductor device of claim 1 wherein said metal silicide region has the same thickness as said source and drain regions.

Claim 5

A semiconductor device comprising: a substrate having an insulating surface; and a plurality of thin film transistors formed on said insulating surface, at least one of said thin film transistors comprising a silicon semiconductor layer including source, drain and channel regions, metal silicide regions connected to said source and drain regions, a gate insulating layer formed on said semiconductor layer, a gate electrode formed on said gate insulating layer, and an oxide insulating layer comprising an oxide of a material of said gate electrode formed on at least side surfaces of said gate electrode wherein said source and drain regions are offset from said gate electrode by a thickness of said oxide insulating layer wherein said at least one of the thin film transistors is provided with side spacers adjacent to the side surfaces of said gate electrode with said oxide insulating layer interposed therebetween, and inner edges of said metal silicide regions are substantially aligned with outer edges of said side spacers.

Claim 6

A semiconductor device comprising: a substrate having an insulating surface; and a plurality of thin film transistors formed on said insulating surface, at least one of said thin film transistors comprising a silicon semiconductor layer including source, drain and channel regions, metal silicide regions connected to said source and drain regions, a gate insulating layer formed on said semiconductor layer, a gate electrode formed on said gate insulating layer, and an oxide insulating layer comprising an oxide of a material of said gate electrode formed on at least side surfaces of said gate electrode wherein said source and drain regions are offset from said gate electrode by a thickness of said oxide insulating layer wherein said at least one of the thin film transistors is provided with side spacers adjacent to the side surfaces of said gate electrode with said oxide insulating layer interposed therebetween, and inner edges of said metal silicide regions are substantially aligned with outer edges of said side spacers.

Claim 7

The device of claim 4 wherein said oxide insulating layer comprises an anodic oxide of the material of said gate electrode.

Claim 8

The semiconductor device of claim 4 wherein said metal is selected from the group consisting of molybdenum (Mo), tungsten (W), platinum (Pt), chromium (Cr), titanium (Ti), and cobalt (Co).

Claim 9

The semiconductor device of claim 4 wherein said metal silicide region has the same thickness as said source and drain regions.

Claim 10

A monolithic circuit comprising: a substrate having an insulating surface, said substrate including an active matrix circuit portion and a peripheral circuit portion; a first plurality of thin film transistors formed on the active matrix circuit portion of the substrate, each of said first plurality of thin film transistors having at least silicon semiconductor layer including source, drain and channel regions therein, an insulated gate electrode formed on said channel region, and an oxide insulating layer comprising an oxide of a material of said gate electrode formed on at least side surfaces of said gate electrode; and a second plurality of thin film transistors formed on the peripheral circuit portion of the substrate for driving said first plurality of thin film transistors, each of said second plurality of thin film transistors having at least silicon semiconductor layer including source, drain and channel regions therein, and an insulated gate electrode adjacent to said channel region, wherein only said first plurality of thin film transistors are provided with metal silicide regions on or in contact with the source and drain regions thereof, and each of said first plurality of thin film transistors is provided with side spacers adjacent to the side surfaces of said gate electrode with said oxide insulating layer interposed therebetween, and inner edges of said metal silicide regions are substantially aligned with outer edges of said side spacers.

Claim 11

A monolithic circuit comprising: a substrate having an insulating surface, said substrate including an active matrix circuit portion and a peripheral circuit portion; a first plurality of thin film transistors formed on the active matrix circuit portion of the substrate, each of said first plurality of thin film transistors having at least silicon semiconductor layer including source, drain and channel regions therein, an insulated gate electrode formed on said channel region, and an oxide insulating layer comprising an oxide of a material of said gate electrode formed on at least side surfaces of said gate electrode; and a second plurality of thin film transistors formed on the peripheral circuit portion of the substrate for driving said first plurality of thin film transistors, each of said second plurality of thin film transistors having at least silicon semiconductor layer including source, drain and channel regions therein, and an insulated gate electrode adjacent to said channel region, wherein only said first plurality of thin film transistors are provided with metal silicide regions on or in contact with the source and drain regions thereof, and each of said first plurality of thin film transistors is provided with side spacers adjacent to the side surfaces of said gate electrode with said oxide insulating layer interposed therebetween, and inner edges of said metal silicide regions are substantially aligned with outer edges of said side spacers.

Claim 12

The monolithic circuit of claim 8 wherein said metal is selected from the group consisting of molybdenum (Mo), tungsten (W), platinum (Pt), chromium (Cr), titanium (Ti), and cobalt (Co).

Claim 13

The monolithic circuit of claim 8 wherein said metal silicide region has the same thickness as said source and drain regions.

Claim 14

The monolithic circuit of claim 8 wherein said second plurality of thin film transistors are not provided with a metal silicide region on or in contact with the source and drain regions thereof.

Claim 15

The monolithic circuit of claim 8 wherein said first plurality of thin film transistors have a larger offset gate area than said second plurality of thin film transistors.

Claim 16

The monolithic circuit of claim 8 wherein said semiconductor layer in said first plurality of thin film transistors is doped with an impurity selected from the group carbon, oxygen and nitrogen at a concentration 5×10 19 -5×10 21 atoms/cm 3 .

Claim 17

The monolithic circuit of claim 8 wherein the gate electrode of said first plurality of thin film transistors is provided with a first oxide of the material of said gate electrode.

Claim 18

The monolithic circuit of claim 14 wherein the gate electrode of said second plurality of thin film transistors is provided with a second oxide of the material of said gate electrode, said second oxide being thinner than said first oxide.

Claim 19

A monolithic circuit comprising: a substrate having an insulating surface, said substrate including an active matrix circuit portion and a peripheral circuit portion; a first plurality of thin film transistors formed on the active matrix circuit portion of the substrate; and a second plurality of thin film transistors formed on the peripheral circuit portion of the substrate for driving said first plurality of thin film transistors, wherein (a) each of said first and second plurality of thin film transistors comprises a silicon semiconductor layer including source, drain and channel regions therein, metal silicide regions connected to said source and drain regions, a gate insulating layer formed on said semiconductor layer, and a gate electrode formed on said gate insulating layer and an oxide insulating layer comprising an oxide of a material of said gate electrode formed on at least side surfaces of said gate electrode; (b) each of said first and second plurality of thin film transistors is provided with side spacers formed adjacent to the side surfaces of said gate electrode with said oxide insulating layer interposed therebetween; and (c) inner edges of said metal silicide regions are substantially aligned with outer edges of said side spacers.

Claim 20

A monolithic circuit comprising: a substrate having an insulating surface, said substrate including an active matrix circuit portion and a peripheral circuit portion; a first plurality of thin film transistors formed on the active matrix circuit portion of the substrate; and a second plurality of thin film transistors formed on the peripheral circuit portion of the substrate for driving said first plurality of thin film transistors, wherein (a) each of said first and second plurality of thin film transistors comprises a silicon semiconductor layer including source, drain and channel regions therein, metal silicide regions connected to said source and drain regions, a gate insulating layer formed on said semiconductor layer, and a gate electrode formed on said gate insulating layer and an oxide insulating layer comprising an oxide of a material of said gate electrode formed on at least side surfaces of said gate electrode; (b) each of said first and second plurality of thin film transistors is provided with side spacers formed adjacent to the side surfaces of said gate electrode with said oxide insulating layer interposed therebetween; and (c) inner edges of said metal silicide regions are substantially aligned with outer edges of said side spacers.

Claim 21

The monolithic circuit of claim 16 wherein said metal is selected from the group consisting of molybdenum (Mo), tungsten (W), platinum (Pt), chromium (Cr), titanium (Ti), and cobalt (Co).

Claim 22

The monolithic circuit of claim 16 wherein said metal silicide region has the same thickness as said source and drain regions.

Claim 23

The device of claim 1 wherein said oxide insulating layer comprises an anodic oxide of the material of said gate electrode.

Claim 24

The monolithic circuit of claim 16 wherein said first plurality of thin film transistors have a larger offset gate area than said second plurality of thin film transistors.

Claim 25

The monolithic circuit of claim 16 wherein said semiconductor in said first plurality of thin film transistors is doped with an impurity selected from the group carbon, oxygen and nitrogen at a concentration 5×10 19 5×10 21 atoms/cm 3 .

Claim 26

The monolithic circuit of claim 16 wherein the gate electrode of said first plurality of thin film transistors is provided with a first oxide of the material of said gate electrode.

Claim 27

The monolithic circuit of claim 22 wherein the gate electrode of said second plurality of thin film transistors is provided with a second oxide of the material of said gate electrode, said second oxide being thinner than said first oxide.

Claim 28

A semiconductor device comprising: a substrate having an insulating surface; a pair of p-channel thin film transistor and an n-channel thin film transistor formed on said insulating surface; each of said p-channel and n-channel thin film transistors having a pair of impurity silicon semiconductor regions, a channel semiconductor region extending therebetween, metal silicide regions connected to said impurity silicon semiconductor regions, a gate insulating layer formed on said channel semiconductor region, a gate electrode formed on said gate insulating layer, and an oxide insulating layer comprising an oxide of a material of said gate electrode formed on at least side surfaces of said gate electrode; and one of the pair of impurity regions of said p-channel thin film transistor being electrically connected with one of the pair of impurity regions of said n-channel thin film transistors through corresponding one of said metal silicide regions formed therebetween, wherein said each of said p-channel and n-channel thin film transistors is provided with side spacers adjacent to the side surfaces of said gate electrode with said oxide insulating layer interposed therebetween, and inner edges of said metal silicide regions are substantially aligned with outer edges of said side spacers.

Claim 29

A semiconductor device comprising: a substrate having an insulating surface; a pair of p-channel thin film transistor and an n-channel thin film transistor formed on said insulating surface; each of said p-channel and n-channel thin film transistors having a pair of impurity silicon semiconductor regions, a channel semiconductor region extending therebetween, metal silicide regions connected to said impurity silicon semiconductor regions, a gate insulating layer formed on said channel semiconductor region, a gate electrode formed on said gate insulating layer, and an oxide insulating layer comprising an oxide of a material of said gate electrode formed on at least side surfaces of said gate electrode; and one of the pair of impurity regions of said p-channel thin film transistor being electrically connected with one of the pair of impurity regions of said n-channel thin film transistors through corresponding one of said metal silicide regions formed therebetween, wherein said each of said p-channel and n-channel thin film transistors is provided with side spacers adjacent to the side surfaces of said gate electrode with said oxide insulating layer interposed therebetween, and inner edges of said metal silicide regions are substantially aligned with outer edges of said side spacers.

Claim 30

The semiconductor device of claim 24 wherein said pair of p-channel thin film transistors and a n-channel thin film transistor form a CMOS circuit.

Claim 31

The semiconductor device of claim 24 wherein an electrode is provided on said metal silicide layer.

Claim 32

The device of claim 1 wherein said source and drain regions extend between said channel region and said metal silicide regions and are substantially coextensive with said side spacers.

Claim 33

The device of claim 4 wherein said source and drain regions extend between said channel region and said metal silicide regions and are substantially coextensive with said side spacers.

Claim 34

The device of claim 24 wherein said metal silicide layer is interposed between said one of the pair of impurity regions of said p-channel thin film transistor and said one of the pair of impurity regions of said n-channel thin film transistors.