US5893741A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for simultaneously forming local interconnect with silicided elevated source/drain MOSFET's
Assignee: National Science and Technology Council
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Filing: 1997-02-07
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Granted: 1999-04-13
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Expires: 2017-02-07
Abstract
Abstract A method for formation of both local innerconnection and silicidation of source/drain transistors using the deposition of a blanket silicon layer over the entire top surface of the transistors and selectively stripping of unwanted portions of the silicon layer is disclosed. The method includes the step of applying a photoresist mask to map out where the local interconnection and source/drain are to be located. The final recited step is to deposit a thin metal layer to provide for the silicidation to complete the transistor. The silicon layer that is deposited has a thickness of 20 to 300 millimeters, and the thin metal layer is either cobalt or titanium having a thickness of 10 millimeters to 100 millimeters.
Inventors
- 👤 Tiao-Yuan Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:59
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0275; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
153 words
A method to provide both local interconnection and silicidation of source/drain transistors comprising the steps of: photolithographic patterning and etching to form a gate structure, forming a sidewall spacer around the gate structure, forming a blanket silicon layer in which single crystal silicon is disposed on an exposed source/drain and polycrystal silicon is disposed on top of an oxidized layer, said gate structure, and side wall spacer, applying a photoresist mask in implanting n + and p + source/drain ions to form a LDD region, selectively stripping off unwanted portions of the silicon layer not protected by photoresist in a local interconnection photomask, wherein the remaining portions are used for local interconnection and source/drain, and depositing a metal layer in which a silicide layer is formed on said polycrystal silicon to form a local interconnection and a silicide is formed on said single crystal silicon of said source/drain to form a silicided source/drain.
Claim 2
Independent Claim
153 words
A method to provide both local interconnection and silicidation of source/drain transistors comprising the steps of: photolithographic patterning and etching to form a gate structure, forming a sidewall spacer around the gate structure, forming a blanket silicon layer in which single crystal silicon is disposed on an exposed source/drain and polycrystal silicon is disposed on top of an oxidized layer, said gate structure, and side wall spacer, applying a photoresist mask in implanting n + and p + source/drain ions to form a LDD region, selectively stripping off unwanted portions of the silicon layer not protected by photoresist in a local interconnection photomask, wherein the remaining portions are used for local interconnection and source/drain, and depositing a metal layer in which a silicide layer is formed on said polycrystal silicon to form a local interconnection and a silicide is formed on said single crystal silicon of said source/drain to form a silicided source/drain.
Claim 3
Dependent Claim
31 words
The method according to claim 1, wherein said blanket silicon layer is grown in a load-lock LPCVD-Si, and said blanket silicon layer has a thickness of 20 nm to 300 nm.
Claim 4
Independent Claim
25 words
The method according to claims 1, wherein the step of selectively stripping is by a CH 3 COOH, HNO 3 , and HF based solution.
Claim 5
Dependent Claim
23 words
The method according to claim 1, wherein the deposited thin metal layer is cobalt having a thickness of 10 nm to 100 nm.
Claim 6
Dependent Claim
23 words
The method according to claim 1, wherein the deposited thin metal layer is titanium having a thickness of 10 nm to 100 nm.
Claim 7
Dependent Claim
18 words
The method according to claim 1, wherein an uppermost portion of said gate structure is WSi 2 /Poly.
Claim 8
Dependent Claim
16 words
The method according to claim 1, wherein an uppermost portion of said gate structure is TiN/Poly.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-12 | 2002-10-12 | 2003-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-12 | 2006-10-12 | 2007-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-12 | 2010-10-12 | 2011-04-13 | $7700.00 | Window Closed / Lapsed |