US5637518A
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US
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Method of making a field effect transistor having an elevated source and an elevated drain
Assignee: Mosaid Technologies Inc
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Filing: 1995-10-16
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Granted: 1997-06-10
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Expires: 2015-10-16
Abstract
Abstract A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, i) produce doped monocrystalline silicon extending outwardly from the substrate surface, and ii) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces. A field effect transistor is also claimed.
Inventors
- 👤 Kirk Prall
- 👤 Pai-Hung Pan
- 👤 Sujit Sharan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:01
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0275; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S438/00; Y10S438/969
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
191 words
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, the transistor having an elevated source and an elevated drain, the method comprising the following steps: providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, a) produce doped monocrystalline silicon extending outwardly from the substrate surface, and b) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces.
Claim 2
Independent Claim
191 words
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, the transistor having an elevated source and an elevated drain, the method comprising the following steps: providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, a) produce doped monocrystalline silicon extending outwardly from the substrate surface, and b) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces.
Claim 3
Dependent Claim
22 words
The method of forming a field effect transistor of claim 1 wherein the non-polycrystalline silicon layer as deposited predominantly comprises amorphous silicon.
Claim 4
Dependent Claim
22 words
The method of forming a field effect transistor of claim 1 wherein the non-polycrystalline silicon layer as deposited predominantly comprises monocrystalline silicon.
Claim 5
Dependent Claim
35 words
The method of forming a field effect transistor of claim 1 wherein the high temperature annealing conditions comprise exposing the substrate to a temperature of from 550° C. to 750° C. in an inert atmosphere.
Claim 6
Dependent Claim
60 words
The method of forming a field effect transistor of claim 1 wherein the step of chemical vapor depositing comprises varying a rate of conductivity enhancing dopant fed to the reactor during deposition from a lower rate to a higher rate to ultimately provide a low to high concentration gradient within the monocrystalline silicon from adjacent the substrate to outwardly therefrom.
Claim 7
Dependent Claim
48 words
The method of forming a field effect transistor of claim 1 wherein the cleaning step is conducted within the same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing step, the substrate not being removed from the reactor between the cleaning and chemical vapor depositing steps.
Claim 8
Dependent Claim
50 words
The method of forming a field effect transistor of claim 1 wherein the high temperature annealing step is conducted within the same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing step, the substrate not being removed from the reactor between the chemical vapor depositing and annealing steps.
Claim 9
Dependent Claim
87 words
The method of forming a field effect transistor of claim 1 wherein, the cleaning step is conducted within the same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing step, the substrate not being removed from the reactor between the cleaning and chemical vapor depositing steps; and the high temperature annealing step is conducted within the same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing step, the substrate not being removed from the reactor between the chemical vapor depositing and annealing steps.
Claim 10
Dependent Claim
97 words
The method of forming a field effect transistor of claim 1 wherein, the step of chemical vapor depositing comprises varying a rate of conductivity enhancing dopant fed to the reactor during deposition from a lower rate to a higher rate to ultimately provide a low to high concentration gradient within the monocrystalline silicon from adjacent the substrate to outwardly therefrom; and the cleaning step is conducted within the same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing step, the substrate not being removed from the reactor between the cleaning and chemical vapor depositing steps.
Claim 11
Dependent Claim
99 words
The method of forming a field effect transistor of claim 1 wherein, the step of chemical vapor depositing comprises varying a rate of conductivity enhancing dopant fed to the reactor during deposition from a lower rate to a higher rate to ultimately provide a low to high concentration gradient within the monocrystalline silicon from adjacent the substrate to outwardly therefrom; and the high temperature annealing step is conducted within the same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing step, the substrate not being removed from the reactor between the chemical vapor depositing and annealing steps.
Claim 12
Dependent Claim
135 words
The method of forming a field effect transistor of claim 1 wherein, the step of chemical vapor depositing comprises varying a rate of conductivity enhancing dopant fed to the reactor during deposition from a lower rate to a higher rate to ultimately provide a low to high concentration gradient within the monocrystalline silicon from adjacent the substrate to outwardly therefrom; the cleaning step is conducted within the same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing step, the substrate not being removed from the reactor between the cleaning and chemical vapor depositing steps; and the high temperature annealing step is conducted within the same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing step, the substrate not being removed from the reactor between the chemical vapor depositing and annealing steps.
Claim 13
Dependent Claim
71 words
The method of forming a field effect transistor of claim 1 wherein, the non-polycrystalline silicon layer as deposited predominantly comprises amorphous silicon; and the step of chemical vapor depositing comprises varying a rate of conductivity enhancing dopant fed to the reactor during deposition from a lower rate to a higher rate to ultimately provide a low to high concentration gradient within the monocrystalline silicon from adjacent the substrate to outwardly therefrom.
Claim 14
Dependent Claim
59 words
The method of forming a field effect transistor of claim 1 wherein, the non-polycrystalline silicon layer as deposited predominantly comprises amorphous silicon; and the cleaning step is conducted within the same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing step, the substrate not being removed from the reactor between the cleaning and chemical vapor depositing steps.
Claim 15
Dependent Claim
61 words
The method of forming a field effect transistor of claim 1 wherein, the non-polycrystalline silicon layer as deposited predominantly comprises amorphous silicon; and the high temperature annealing step is conducted within the same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing step, the substrate not being removed from the reactor between the chemical vapor depositing and annealing steps.
Claim 16
Dependent Claim
97 words
The method of forming a field effect transistor of claim 1 wherein, the non-polycrystalline silicon layer as deposited predominantly comprises amorphous silicon; the cleaning step is conducted within the same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing step, the substrate not being removed from the reactor between the cleaning and chemical vapor depositing steps; and the high temperature annealing step is conducted within the same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing step, the substrate not being removed from the reactor between the chemical vapor depositing and annealing steps.
Claim 17
Dependent Claim
145 words
The method of forming a field effect transistor of claim 1 wherein, the non-polycrystalline silicon layer as deposited predominantly comprises amorphous silicon; the step of chemical vapor depositing comprises varying a rate of conductivity enhancing dopant fed to the reactor during deposition from a lower rate to a higher rate to ultimately provide a low to high concentration gradient within the monocrystalline silicon from adjacent the substrate to outwardly therefrom; the cleaning step is conducted within the same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing step, the substrate not being removed from the reactor between the cleaning and chemical vapor depositing steps; and the high temperature annealing step is conducted within the same rapid thermal chemical vapor deposition reactor as the chemical vapor depositing step, the substrate not being removed from the reactor between the chemical vapor depositing and annealing steps.
Claim 18
Independent Claim
169 words
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, the transistor having an elevated source and an elevated drain, the method comprising the following steps: providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; and within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a monocrystalline doped silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing, the step of chemical vapor depositing comprises varying a rate of conductivity enhancing dopant fed to the reactor during deposition from a lower rate to a higher rate to ultimately provide a low to high concentration gradient within the monocrystalline silicon from adjacent the substrate to outwardly therefrom.
Claim 19
Independent Claim
169 words
A method of forming a field effect transistor relative to a monocrystalline silicon substrate, the transistor having an elevated source and an elevated drain, the method comprising the following steps: providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; and within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a monocrystalline doped silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing, the step of chemical vapor depositing comprises varying a rate of conductivity enhancing dopant fed to the reactor during deposition from a lower rate to a higher rate to ultimately provide a low to high concentration gradient within the monocrystalline silicon from adjacent the substrate to outwardly therefrom.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-09 | 2000-12-09 | 2001-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-09 | 2004-12-09 | 2005-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-09 | 2008-12-09 | 2009-06-10 | $7700.00 | Window Closed / Lapsed |