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US5880483A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor devices

Assignee: OL Security LLC
•
Filing: 1993-02-23
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Granted: 1999-03-09
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Expires: 2013-02-23
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Abstract

Abstract A field effect transistor having a substrate supporting an active layer comprising a Group III-V material. The active layer has a dopant concentration with a source electrode and a drain electrode disposed over and with a gate electrode disposed between the source and drain electrodes in Schottky barrier contact to the active layer. A surface layer portion of the active layer has a negatively charged surface potential disposed between the drain and gate electrodes comprised of said Group III-V material and oxygen. The surface layer portion has a thickness in the range of 25 Å to 35 Å. A layer of passivation material is disposed at least on the surface layer portion of the active layer.

Inventors

  • 👤 Stanley R. Shanfield
  • 👤 Bharat Patel
  • 👤 Hermann Statz

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 10:09
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/80; H10D30/87; H10D30/877; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/161; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/65; H10P14/6502; H10P14/6512; H10P14/6514; H10P14/66; H10P14/668; H10P14/6681; H10P14/6682; H10P14/68; H10P14/683; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/6922; H10P14/6927; H10P14/694; H10P14/6943; H10P14/69433

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 112 words
A field effect transistor comprising: a substrate supporting an active layer comprising a Group III-V material having a dopant concentration with a source electrode and a drain electrode disposed thereover and with a gate electrode disposed between said source and drain electrodes in Schottky barrier contact to said active layer; a surface layer portion of said active layer having anions to provide a negatively charged surface potential disposed between said drain and gate electrodes comprised of said Group III-V material and oxygen having a thickness in the range of 25 Å to 35 Å; and a layer of passivation material disposed at least on said surface layer portion of said active layer.
Claim 2
Dependent Claim 112 words
A field effect transistor comprising: a substrate supporting an active layer comprising a Group III-V material having a dopant concentration with a source electrode and a drain electrode disposed thereover and with a gate electrode disposed between said source and drain electrodes in Schottky barrier contact to said active layer; a surface layer portion of said active layer having anions to provide a negatively charged surface potential disposed between said drain and gate electrodes comprised of said Group III-V material and oxygen having a thickness in the range of 25 Å to 35 Å; and a layer of passivation material disposed at least on said surface layer portion of said active layer.
Claim 3
Dependent Claim 19 words
The field effect transistor, as recited in claim 1, wherein said surface layer portion has a substantially uniform thickness.
Claim 4
Dependent Claim 29 words
The field effect transistor, as recited in claim 1, wherein said passivation layer selected from the group consisting of silicon nitride, silicon dioxide, silicon monoxide, silicon oxynitride, and polyamide.
Claim 5
Dependent Claim 16 words
The field effect transistor, as recited in claim 1, wherein said passivation layer is silicon nitride.
Claim 6
Dependent Claim 142 words
A field effect transistor comprising: a substrate of gallium arsenide having an active layer comprising doped gallium arsenide with the dopant having a concentration in the range 1×10 16 to 5×10 17 a/cc, having source and drain electrodes disposed thereover with a gate electrode disposed between said source and drain electrodes and in Schottky barrier contact to said active layer; a surface layer portion of said doped gallium arsenide active layer having anions to provide a negatively charged surface potential disposed between said drain and gate electrodes, said surface layer portion comprised of an oxide of said gallium arsenide and having a thickness of at least 25 Å; and a layer of a passivation material selected from the group consisting of silicon nitride, silicon dioxide, silicon monoxide, silicon oxynitride, and polymide disposed on at least said surface portion of said active layer.
Claim 7
Dependent Claim 142 words
A field effect transistor comprising: a substrate of gallium arsenide having an active layer comprising doped gallium arsenide with the dopant having a concentration in the range 1×10 16 to 5×10 17 a/cc, having source and drain electrodes disposed thereover with a gate electrode disposed between said source and drain electrodes and in Schottky barrier contact to said active layer; a surface layer portion of said doped gallium arsenide active layer having anions to provide a negatively charged surface potential disposed between said drain and gate electrodes, said surface layer portion comprised of an oxide of said gallium arsenide and having a thickness of at least 25 Å; and a layer of a passivation material selected from the group consisting of silicon nitride, silicon dioxide, silicon monoxide, silicon oxynitride, and polymide disposed on at least said surface portion of said active layer.
Claim 8
Dependent Claim 163 words
A field effect transistor comprising: a substrate; an active layer supported on said substrate comprising a Group III-V material having a dopant; source and drain gate electrodes disposed in ohmic contact over the active layer; a gate electrode disposed in Schottky barrier contact to said active layer and between said source and drain electrodes; a surface layer portion of said active layer having anions to provide a negatively charged surface potential disposed between an edge portion of each of said source and drain electrodes, said edge portion proximate to a corresponding adjacent edge of said gate electrode, and not on a portion of said active layer underlying said source, drain and gate electrodes, said surface layer portion comprised of said Group III-V material and oxygen and having a thickness in the range of 25 Å to 35 Å; and a layer of passivation material different than the material of said surface layer portion, disposed over said surface layer portion of said active layer.
Claim 9
Dependent Claim 163 words
A field effect transistor comprising: a substrate; an active layer supported on said substrate comprising a Group III-V material having a dopant; source and drain gate electrodes disposed in ohmic contact over the active layer; a gate electrode disposed in Schottky barrier contact to said active layer and between said source and drain electrodes; a surface layer portion of said active layer having anions to provide a negatively charged surface potential disposed between an edge portion of each of said source and drain electrodes, said edge portion proximate to a corresponding adjacent edge of said gate electrode, and not on a portion of said active layer underlying said source, drain and gate electrodes, said surface layer portion comprised of said Group III-V material and oxygen and having a thickness in the range of 25 Å to 35 Å; and a layer of passivation material different than the material of said surface layer portion, disposed over said surface layer portion of said active layer.
Claim 10
Dependent Claim 24 words
The field effect transistor recited in claim 1 wherein the passivation layer is disposed on, and in direct contact with the negatively charged surface.
Claim 11
Dependent Claim 24 words
The field effect transistor recited in claim 5 wherein the passivation layer is disposed on, and in direct contact with the negatively charged surface.
Claim 12
Dependent Claim 24 words
The field effect transistor recited in claim 6 wherein the passivation layer is disposed on, and in direct contact with the negatively charged surface.

References Cited (Backward Citations)

US4062747A Cited
US4688062A Cited
US4843450A Cited
US5021365A Cited
US4990984A Cited
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US5008719A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-03-08 2002-09-07 2003-03-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-03-08 2006-09-07 2007-03-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-03-08 2010-09-07 2011-03-09 $7700.00 Window Closed / Lapsed

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