Semiconductor structure and method of manufacture

Claim 1

A field effect transistor having gate, drain and source electrodes comprising: a substrate comprising gallium arsenide, said substrate having crystal defects which provide electron and hole traps; a doped buffer layer disposed over said substrate and comprising a gallium arsenide crystal layer having acceptor energy levels intermediate valence and conduction bands of said crystal layer provided by doping said crystalline layer with chromium to compensate for donor energy levels provided by dopants incorporated into said crystalline layer to provide said layer having a predetermined resistivity characteristic; a shielding layer disposed over the doped buffer layer comprising a layer of gallium arsenide over said buffer layer having an electron concentration substantially in the range of 10 14 to 3×10 15 electrons/cm 3 ; an active layer comprising gallium arsenide having a dopant concentration of about 10 17 electron/cm 3 , disposed over said shielding layer; a gate electrode disposed in Schottky-barrier contact with a portion of said active layer; a contact layer disposed over portion of said active layer and comprising a highly doped layer of gallium arsenide selected to provide ohmic contact region for drain and source electrodes; and wherein the electron concentration in the shielding layer provides a small predetermined conduction in said shielding layer to isolate the active layer from a net ionization of said chromium dopant in the buffer layer provided in response to a current flux between drain and source electrodes and from a net ionization of the electron and hole traps provided in said substrate.