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US5879998A
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Adaptively controlled, self-aligned, short channel device and method for manufacturing same
Assignee: GlobalFoundries Inc
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Filing: 1997-07-09
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Granted: 1999-03-09
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Expires: 2017-07-09
Abstract
Abstract A short channel semiconductor device having source and drain regions in a substrate and a gate region on the top surface of the substrate between the source and drain regions is disclosed. In one embodiment, the method comprises: forming a device area in the silicon by forming a pattern stack, and forming pattern spacers adjacent to the pattern stack; forming a trench isolation about the pattern stack; removing the pattern spacers; depositing an epitaxial layer over the trench oxide and adjacent to the pattern stack; removing the pattern stack; and forming adaptively controlled spacers in the region to control said short channel length of the device. The apparatus of the present invention comprises: a semiconductor substrate; a source region and a drain region formed in the substrate; a gate region, comprising a first and a second oxide regions, a first control spacer and a second control spacer positioned above the substrate and adjacent to the first and second oxide regions, respectively, and a polysilicon layer positioned between the spacers; and an epitaxial layer, adjacent to the source and drain region and surrounding said first and second spacers.
Inventors
- 👤 Zoran Krivokapic
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:30
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/027; H10D30/0275; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01324; H10D64/01326; H10D64/017; H10D64/018; H10D64/021; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/10; H10W10/17; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; H10D30/0212; H10D30/0217
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
100 words
A method of manufacturing a short channel semiconductor device, comprising: (A) forming a device area in the silicon by: (1) forming a pattern stack; (2) forming pattern spacers adjacent to the pattern stack; (B) forming a trench isolation about the pattern stack; (C) removing the pattern spacers; (D) depositing an epitaxial layer over the trench isolation and adjacent to the pattern stack; (E) removing the pattern stack to define a device region; and (F) forming channel control spacers in the device region, each channel control spacer having a width selected to control a channel length in said short channel device.
Claim 2
Independent Claim
100 words
A method of manufacturing a short channel semiconductor device, comprising: (A) forming a device area in the silicon by: (1) forming a pattern stack; (2) forming pattern spacers adjacent to the pattern stack; (B) forming a trench isolation about the pattern stack; (C) removing the pattern spacers; (D) depositing an epitaxial layer over the trench isolation and adjacent to the pattern stack; (E) removing the pattern stack to define a device region; and (F) forming channel control spacers in the device region, each channel control spacer having a width selected to control a channel length in said short channel device.
Claim 3
Dependent Claim
14 words
The method of claim 1 wherein said control spacers are composed of a nitride.
Claim 4
Dependent Claim
20 words
The method of claim 2 wherein said control spacers have a width of between about 0.05 μm and 0.15 μm.
Claim 5
Dependent Claim
94 words
The method of claim 1 wherein said step A(1) comprises the sub-steps of: sequentially depositing a first oxide layer, a first nitride layer, a second oxide layer and a second nitride layer on said substrate, each said layer having a layer length, a layer width and a layer height, said second nitride layer having a second nitride layer top surface; masking the layer length of said first and second oxide layers and said first and second nitride layers; and etching the first oxide layer, first nitride layer, second nitride layer and second oxide layer.
Claim 6
Dependent Claim
30 words
The method of claim 1 wherein said step (A)(2) comprises the sub-steps of: (i) forming oxide spacers about the pattern stack; and (ii) forming nitride spacers about the oxide spacers.
Claim 7
Dependent Claim
80 words
The method of claim 5 wherein: said step (i) comprises: forming a first oxide spacer layer along the pattern stack, said first oxide spacer layer having a first oxide spacer lateral surface, selectively masking said first spacer oxide layer, and etching said first oxide spacer layer; and said step (ii) comprises: forming a first nitride spacer layer along the pattern stack, said first nitride spacer layer having a first nitride spacer lateral surface, and etching said first nitride spacer layer.
Claim 8
Dependent Claim
46 words
The method of claim 1 wherein said step (B) comprises: forming an oxide trench into said substrate; depositing a trench oxide into said oxide trench, said trench oxide having a trench oxide top surface; and polishing the trench oxide top surface to said second nitride layer.
Claim 9
Dependent Claim
31 words
The method of claim 1, further including the step, between said steps (B) and (C), of: removing a portion of the trench oxide layer to form a lowered trench oxide layer.
Claim 10
Dependent Claim
29 words
The method of claim 1 further including the step of: (G) forming a source and drain region by depositing an impurity into the epitaxial layer and heating the substrate.
Claim 11
Dependent Claim
23 words
The method of claim 9 further including the step of: (H) forming a local interconnect layer coupled to said source and drain regions.
Claim 12
Dependent Claim
20 words
The method of claim 1 wherein said control spacers have a width of between about 0.05 μm and 0.15 μm.
Claim 13
Independent Claim
260 words
A method for making a semiconductor device, comprising: (A) sequentially depositing a first oxide layer, a first nitride layer, a second oxide layer and a second nitride layer on said substrate, each said layer having a layer length, a layer width and a layer height, said second nitride layer having a second nitride layer top surface; (B) etching the layer length of said first and second oxide layers and said first and second nitride layers to form pattern stack on the surface of the substrate; (C) forming a first oxide spacer along the pattern stack; (D) forming a first nitride spacer along the first oxide spacer; (E) etching an oxide trench into said substrate; (F) depositing a trench oxide into said oxide trench; (G) etching said trench oxide, said second nitride layer and said first nitride spacer layer to remove said second nitride layer and said first nitride spacer layer and form a lowered trench oxide having a lowered trench oxide top surface; (H) forming a selective epitaxial overgrowth layer on said lowered trench oxide top surface and on said substrate; (I) removing said second oxide layer, said first nitride layer and said first oxide spacer layer to form a gate region, said gate region having gate region sidewalls adjacent to said selective epitaxial overgrowth layer and a gate region bottom overlying said first oxide layer; (J) selectively depositing control spacers within said gate region; and (K) implanting an impurity into the epitaxial layer and diffusing the impurity to form a source region and a drain region within said substrate.
Claim 14
Independent Claim
260 words
A method for making a semiconductor device, comprising: (A) sequentially depositing a first oxide layer, a first nitride layer, a second oxide layer and a second nitride layer on said substrate, each said layer having a layer length, a layer width and a layer height, said second nitride layer having a second nitride layer top surface; (B) etching the layer length of said first and second oxide layers and said first and second nitride layers to form pattern stack on the surface of the substrate; (C) forming a first oxide spacer along the pattern stack; (D) forming a first nitride spacer along the first oxide spacer; (E) etching an oxide trench into said substrate; (F) depositing a trench oxide into said oxide trench; (G) etching said trench oxide, said second nitride layer and said first nitride spacer layer to remove said second nitride layer and said first nitride spacer layer and form a lowered trench oxide having a lowered trench oxide top surface; (H) forming a selective epitaxial overgrowth layer on said lowered trench oxide top surface and on said substrate; (I) removing said second oxide layer, said first nitride layer and said first oxide spacer layer to form a gate region, said gate region having gate region sidewalls adjacent to said selective epitaxial overgrowth layer and a gate region bottom overlying said first oxide layer; (J) selectively depositing control spacers within said gate region; and (K) implanting an impurity into the epitaxial layer and diffusing the impurity to form a source region and a drain region within said substrate.
Claim 15
Dependent Claim
23 words
The method of claim 12 further including the step, following step (J), of implanting an impurity to form a threshold voltage implant region.
Claim 16
Dependent Claim
24 words
The method of claim 12 further including the step, following step (J), of implanting an impurity to form a punch through stop implant region.
Claim 17
Dependent Claim
51 words
The method of claim 12 further including the steps, following step (J), of: (J1) forming gate oxide layer; (J2) depositing a polysilicon layer within said gate region, said polysilicon layer being adjacent to said adaptively controlled spacers; and (J3) polishing said polysilicon layer to a level coincident with the control spacers.
Claim 18
Dependent Claim
34 words
The method of claim 12 wherein said step (C) comprises depositing a spacer oxide layer and selectively masking said spacer oxide layer, said first oxide spacer layer having a first oxide spacer lateral surface.
Claim 19
Dependent Claim
34 words
The method of claim 12 wherein said step (D) comprises depositing a spacer nitride layer and selectively masking said spacer nitride layer, said first nitride spacer layer having a first nitride spacer lateral surface.
Claim 20
Dependent Claim
37 words
The method of claim 12, further including the step, after step (J), of implanting an impurity into the epitaxial layer s within said substrate, said implants including a threshold voltage implant and a punch through stop implant.
Claim 21
Dependent Claim
86 words
The method of claim 12 further including the steps, following step J, of: (J1) forming implants within said substrate, said implants including a threshold voltage implant and a punch through stop implant; (J2) forming gate oxide layer; (J3) depositing a polysilicon layer within said gate region, said polysilicon layer being adjacent to said adaptively controlled spacers; (J4) polishing said polysilicon layer to said third oxide layer; and (J5) forming source and drain regions overlapping said gate region by implanting a first conductivity type into said substrate.
Claim 22
Dependent Claim
22 words
The method of claim 12, further including the step of: forming a local interconnect layer above said final selective epitaxial overgrowth layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-08 | 2002-09-07 | 2003-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-08 | 2006-09-07 | 2007-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-08 | 2010-09-07 | 2011-03-09 | $7700.00 | Window Closed / Lapsed |