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US5116780A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing a semiconductor device having improved contact resistance characteristics

Assignee: Toshiba Corp
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Filing: 1990-10-16
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Granted: 1992-05-26
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Expires: 2010-10-16
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Abstract

Abstract A multi-layered insulation film of non-doped CVD SiO 2 (silicon dioxide) film and BPSG (boro-phospho-silicate glass) film is formed on a silicon substrate. Films have a contact hole exposing impurity diffused region formed in silicon substrate. A semiconductor layer is formed in the contact hole. An Al (aluminum) film is formed on the semiconductor layer. The semiconductor layer contacts the BPSG film so that the contact resistance between the semiconductor layer and the Al (aluminum) film can be reduced, and a variation of the contact resistance between respective semiconductor devices can also be reduced.

Inventors

  • 👤 Shuichi Samata
  • 👤 Yoshiaki Matsushita

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 04:43
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/057; H10D; H10D62/00; H10D62/80; H10D62/83; H10D62/834; H10D64/00; H10D64/60; H10D64/62; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10W20/071; H10W20/081

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 217 words
A method of manufacturing a semiconductor device comprising: forming an impurity diffused region of n-conductivity type in a silicon substrate comprising a semiconductor body of p-conductivity type; forming a superposed insulation film structure comprising a first insulation layer and a second insulation layer comprising a film of a component selected from the group consisting of phospho-silicate glass, arseno-silicate glass, boro-phospho-silicate glass, boro-arseno-silicate glass, phospho-arseno-silicate glass, and boro-phospho-arseno-silicate glass, said first insulation layer being formed on said semiconductor body, and said second insulation layer being formed on said semiconductor body, and said second insulation layer being formed on said first insulation layer and containing impurities of n-conductivity type; forming in said first and second insulation layers a continuous contact hole opening onto said impurity diffused region; forming a single crystalline semiconductor silicon layer of said n-conductivity type in said contact hole of said first and second insulation layers by an epitaxial growth process, with the single crystalline semiconductor silicon layer contacting said second insulation layer to diffuse said impurities from said second insulation layer into said single crystalline semiconductor silicon layer during said epitaxial growth process to increase an impurity concentration in a surface region thereof while said first insulation layer prevents impurity diffusion into the silicon substrate; and forming a conductive layer on said semiconductor silicon layer.
Claim 2
Independent Claim 217 words
A method of manufacturing a semiconductor device comprising: forming an impurity diffused region of n-conductivity type in a silicon substrate comprising a semiconductor body of p-conductivity type; forming a superposed insulation film structure comprising a first insulation layer and a second insulation layer comprising a film of a component selected from the group consisting of phospho-silicate glass, arseno-silicate glass, boro-phospho-silicate glass, boro-arseno-silicate glass, phospho-arseno-silicate glass, and boro-phospho-arseno-silicate glass, said first insulation layer being formed on said semiconductor body, and said second insulation layer being formed on said semiconductor body, and said second insulation layer being formed on said first insulation layer and containing impurities of n-conductivity type; forming in said first and second insulation layers a continuous contact hole opening onto said impurity diffused region; forming a single crystalline semiconductor silicon layer of said n-conductivity type in said contact hole of said first and second insulation layers by an epitaxial growth process, with the single crystalline semiconductor silicon layer contacting said second insulation layer to diffuse said impurities from said second insulation layer into said single crystalline semiconductor silicon layer during said epitaxial growth process to increase an impurity concentration in a surface region thereof while said first insulation layer prevents impurity diffusion into the silicon substrate; and forming a conductive layer on said semiconductor silicon layer.
Claim 3
Dependent Claim 31 words
A method of manufacturing a semiconductor device according to claim 1, in which a concentration of impurity of said single crystal semiconductor layer is higher than 4×10 18 cm -3 .
Claim 4
Dependent Claim 20 words
A method of manufacturing a semiconductor device according to claim 1, in which said conductive layer is an aluminum layer.
Claim 5
Dependent Claim 32 words
A method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a second conductive layer between said single crystalline semiconductor silicon layer and said conductive layer.
Claim 6
Dependent Claim 35 words
A method of manufacturing a semiconductor device according to claim 4, in which said second conductive layer is a layer formed of a component selected from the group consisting of molybdenum, titanium, tungsten and tantalum.
Claim 7
Dependent Claim 27 words
A method of manufacturing a semiconductor device according to claim 4, in which said second conductive layer is a layer formed of an alloy titanium and molybdenum.
Claim 8
Dependent Claim 39 words
A method of manufacturing a semiconductor device according to claim 4, in which said second conductive layer is a layer formed of a component selected from the group consisting of molybdenum silicide, titanium silicide, tungsten silicide and tantalum silicide.
Claim 9
Dependent Claim 24 words
A method of manufacturing a semiconductor device according to claim 4, in which said second conductive layer is a layer formed of titanium nitride.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-05-26 1995-11-25 1996-05-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-05-26 1999-11-25 2000-05-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-05-26 2003-11-25 2004-05-26 $7700.00 Window Closed / Lapsed

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