Submicron FET structure and method of making

Claim 1

An integrated circuit field effect transistor structure comprising: a semiconductor body with a surface region; a first insulator layer disposed over said surface region; a substantially horizontal conductive layer disposed over said first insulator layer and having a plurality of different patterns formed therein; a trench opening in said conductive layer and said first insulator layer down to said semiconductor body and having substantially vertical sidewalls; a pair of vertical conformal conductive sidewall layers disposed conformally only on one set of opposite vertical sidewalls of said trench and not electrically connected and containing a dopant with a first conductivity type therein suitable for outdiffusion, said vertical conformal conductive sidewall layers being in electrical contact with different patterns in said substantially horizontal conductive layer; a source region formed in said semiconductor substrate substantially only directly below one of said vertical conformal conductive sidewall layers and having a dopant with said first conductivity type; a drain region formed in said semiconductor substrate substantially only directly below the other of said vertical conformal conductive sidewall layers and having a dopant with said first conductivity type; a second substantially vertical insulator layer disposed conformally on said vertical conformal conductive sidewall layers, and a second horizontal insulator layer disposed conformally in said trench opening, with said second horizontal insulator layer having therein a dopant of said first conductivity type suitable for outdiffusion; a pair of third substantially vertical conformal insulator sidewall layers disposed conformally only on said second substantially vertical insulator layer down to said second horizontal insulator layer; a channel opening down to said semiconductor body in said second horizontal insulator layer in said trench opening and between said pair of third substantially vertical conformal insulator sidewall layers; a doped region disposed in said semiconductor body substantially only below each of said third substantially vertical conformal insulator sidewall layers, with said doped regions having a dopant of first conductivity type but with a lower doping concentration than the doping in said source and drain regions; a gate dielectric disposed in said channel opening; a gate electrode disposed on said gate dielectric; and electrical ohmic contacts connected to said patterns in said substantially horizontal conductive layer.