Sub-micrometer channel length field effect transistor process

Claim 1

A method for fabricating a semiconductor integrated circuit structure having a sub-micrometer width device element comprising: providing a semiconductor substrate; forming a surface isolation pattern in said semiconductor substrate which isolates regions of said semiconductor within said substrate from one another and which regions are designated to contain devices; forming at least one layer over said regions designated to contain devices; etching said at least one layer so as to result in a patterned layer having substantially vertical sidewalls some of which sidewalls extend across certain of said regions designated to contain devices; forming a controlled sub-micrometer thickness layer on said sidewalls; removing by etching said patterned layer which leaves a pattern of controlled sub-micrometer thickness layer portions of which extend across said certain of said regions; and forming the desired pattern of PN junctions in said substrate using said controlled sub-micrometer layer as a mask.

Claim 2

A method for fabricating a semiconductor integrated circuit structure having a sub-micrometer width device element comprising: providing a semiconductor substrate; forming a surface isolation pattern in said semiconductor substrate which isolates regions of said semiconductor within said substrate from one another and which regions are designated to contain devices; forming at least one layer over said regions designated to contain devices; etching said at least one layer so as to result in a patterned layer having substantially vertical sidewalls some of which sidewalls extend across certain of said regions designated to contain devices; forming a controlled sub-micrometer thickness layer on said sidewalls; removing by etching said patterned layer which leaves a pattern of controlled sub-micrometer thickness layer portions of which extend across said certain of said regions; and forming the desired pattern of PN junctions in said substrate using said controlled sub-micrometer layer as a mask.

Claim 11

A method for fabricating a semiconductor integrated circuit structure having at least some field effect transistor devices having a narrow gate width comprising: providing a semiconductor substrate; forming a surface isolation pattern in said semiconductor substrate which isolates regions of said semiconductor within said substrate from one another and which regions are designated to contain devices; forming an insulating layer which is designated to be in part the gate dielectric layer upon the surface of said substrate having the surface isolation pattern therein; depositing a conductive layer upon said insulating layer; depositing a silicon nitride layer on said conductive layer; depositing a polycrystalline silicon layer upon said silicon nitride layer; etching said polycrystalline silicon layer so as to provide portions of said layer having substantial vertical sidewalls; portions of said polycrystalline silicon layer extend across certain of said regions designated to contain devices and unto the surrounding isolation pattern; depositing a conformal insulating layer over said portions; anisotropically etching said conformal layer to substantially remove said layer from horizontal surfaces and leave said conformal layer on said substantially vertical sidewalls of said polycrystalline silicon layer; etching said remaining polycrystalline silicon layer; removing the undesired portions of said conformal sidewall layer; using said conformal sidewall layer as a mask, etching the silicon nitride layer and said conductive layer to form the gate electrodes of said field effect transistor devices in said conductive layer having the width of said conformal sidewall layer; ion implanting conductivity imparting impurities adjacent to said gate electrode to form the desired source/drain element for said field effect devices into said regions designated to contain devices; forming an insulator layer over said devices with openings therein; and forming electrical contacts to the said source/drain and said gate electrode elements of said devices.

Claim 12

A method for fabricating a semiconductor integrated circuit structure having at least some field effect transistor devices having a narrow gate width comprising: providing a semiconductor substrate; forming a surface isolation pattern in said semiconductor substrate which isolates regions of said semiconductor within said substrate from one another and which regions are designated to contain devices; forming an insulating layer which is designated to be in part the gate dielectric layer upon the surface of said substrate having the surface isolation pattern therein; depositing a conductive layer upon said insulating layer; depositing a silicon nitride layer on said conductive layer; depositing a polycrystalline silicon layer upon said silicon nitride layer; etching said polycrystalline silicon layer so as to provide portions of said layer having substantial vertical sidewalls; portions of said polycrystalline silicon layer extend across certain of said regions designated to contain devices and unto the surrounding isolation pattern; depositing a conformal insulating layer over said portions; anisotropically etching said conformal layer to substantially remove said layer from horizontal surfaces and leave said conformal layer on said substantially vertical sidewalls of said polycrystalline silicon layer; etching said remaining polycrystalline silicon layer; removing the undesired portions of said conformal sidewall layer; using said conformal sidewall layer as a mask, etching the silicon nitride layer and said conductive layer to form the gate electrodes of said field effect transistor devices in said conductive layer having the width of said conformal sidewall layer; ion implanting conductivity imparting impurities adjacent to said gate electrode to form the desired source/drain element for said field effect devices into said regions designated to contain devices; forming an insulator layer over said devices with openings therein; and forming electrical contacts to the said source/drain and said gate electrode elements of said devices.