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Patent US5877066A successfully refreshed from Google Patents.
US5877066A
Expired / Lapsed
US
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Narrow width trenches for field isolation in integrated circuits
Assignee: Advanced Micro Devices Inc
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Filing: 1997-11-04
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Granted: 1999-03-02
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Expires: 2017-11-04
Abstract
Abstract An integrated circuit device has a plurality of active devices which are formed on a semiconductor body. A plurality of narrow isolating regions of insulating material are vertically formed on the semiconductor body such that at least one of the narrow isolating regions separates and thereby isolates adjacent active devices. Essentially all of said isolating regions are substantially equal in width, preferably less than or equal to about 0.5 μm.
Inventors
- 👤 Andre Stolmeijer
- 👤 Farrokh Omid-Zohoor
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:42
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
142 words
A method of forming isolating trenches in a semiconductor body containing a plurality of active devices comprising the steps of: forming, by removing portions of said semiconductor body between adjacent active devices, at least a pair of narrow vertical openings spaced apart and separated by a region of the semiconductor body, wherein said region of semiconductor body contains no active devices, essentially all of said openings being formed substantially equal in width; filling said openings with an insulating material to create at least a pair of spaced apart narrow isolating trenches between the adjacent active devices; and adding an impurity of the same type but of a higher concentration as the semiconductor body to the region between the pair of trenches extending from the surface of the semiconductor body between the pair of trenches, thereby providing junction as well as insulating isolation.
Claim 2
Independent Claim
142 words
A method of forming isolating trenches in a semiconductor body containing a plurality of active devices comprising the steps of: forming, by removing portions of said semiconductor body between adjacent active devices, at least a pair of narrow vertical openings spaced apart and separated by a region of the semiconductor body, wherein said region of semiconductor body contains no active devices, essentially all of said openings being formed substantially equal in width; filling said openings with an insulating material to create at least a pair of spaced apart narrow isolating trenches between the adjacent active devices; and adding an impurity of the same type but of a higher concentration as the semiconductor body to the region between the pair of trenches extending from the surface of the semiconductor body between the pair of trenches, thereby providing junction as well as insulating isolation.
Claim 3
Dependent Claim
24 words
The method according to claim 1, wherein the width of each of said isolating trenches is less than or equal to about 0.5 μm.
Claim 4
Dependent Claim
112 words
The method according to claim 1, wherein at least a portion of said active devices are CMOS devices, each with a N-type transistor in a P semiconductor body and a P-type transistor in a N semiconductor body and having a boundary therebetween and at least three spaced apart isolating trenches are formed between the N-type and P-type transistors of each of the CMOS devices, one of the three trenches being positioned at said boundary and being between the other two trenches and each of the other two trenches being separated by a region of the semiconductor body, the impurity of the separated regions being of the same type as the semiconductor body.
Claim 5
Dependent Claim
24 words
The method according to claim 3 wherein said trench positioned at said boundary is formed to be approximately centered between the other two trenches.
Claim 6
Dependent Claim
39 words
The method according to claim 4 wherein the impurity in the regions between the three isolating trenches is P+ in the P semiconductor body and N+ in the N semiconductor body, thereby providing junction as well as insulating isolation.
Claim 7
Dependent Claim
24 words
The method according to claim 5, wherein the width of each of said isolating trenches is less than or equal to about 0.5 μm.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-01 | 2002-08-31 | 2003-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-01 | 2006-08-31 | 2007-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-01 | 2010-08-31 | 2011-03-02 | $7700.00 | Window Closed / Lapsed |