Patent US5874782A successfully refreshed from Google Patents.
US5874782A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wafer with elevated contact structures
Assignee: International Business Machines Corp
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Filing: 1995-08-24
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Granted: 1999-02-23
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Expires: 2015-08-24
Abstract
Abstract Disclosed is a semiconductor wafer, and the method of making the same, the wafer being formed to have a multiplicity of raised contact pads on its surface. The contact pads are formed with conductors which are disposed on the surface of the wafer and which are coupled to internal circuitry embedded in the wafer through vias in the wafer's surface. The contact pads are in a raised elevational relationship relative to the surface conductors. After the wafer is fully processed, by dicing individual integrated circuit chips out of the wafer, each chip can then be mounted on a higher level of assembly, such as a printed circuit board. The raised contact pads originally formed on the wafer, and therefore formed on each individual chip, provide the contact points by which the chip can be bonded with matingly arranged contact pads on the higher level of assembly.
Inventors
- 👤 Anthony Michael Palagonia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 19:04
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/01; H10W74/012; H10W72/00; H10W72/20; H10W72/01; H10W72/012; H10W74/10; H10W74/15; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/654; H10W70/655; H10W72/221; H10W72/241; H10W72/245; H10W72/251; H10W72/253; H10W72/255; H10W72/29; H10W72/851; H10W72/853; H10W72/856; H10W72/90; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W72/952; H10W90/00; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
215 words
An apparatus having a plurality of semiconductor devices comprising: a substrate for mounting an integrated circuit chip, said substrate having contact elements; an integrated circuit chip having a length and width with a central portion along its longitudinal axis with a first and second set of via contacts, having a plurality of surface conductors on a layer of insulative material being at a pre-determined elevation and electrically coupled to said first and second set of via contacts which are electrically connected to the semiconductor devices and said via contacts are spaced apart and centrally disposed along a first and second line that are parallel along the longitudinal axis, alternating via contacts in the first and second set of via contacts are interconnected respectively to a first and second surface conductors which run the length of the chip within the first and second line to form a first and second bus and said chip further having conductive pads coupled to said surface conductors, said conductive pads formed on an insulative bump on top of the layer of insulative coating material such that the pads are at an elevation different from the elevation of said surface conductors; and said chip being coupled to said substrate by means of said conductive pads being bonded to said contact elements.
Claim 2
Independent Claim
215 words
An apparatus having a plurality of semiconductor devices comprising: a substrate for mounting an integrated circuit chip, said substrate having contact elements; an integrated circuit chip having a length and width with a central portion along its longitudinal axis with a first and second set of via contacts, having a plurality of surface conductors on a layer of insulative material being at a pre-determined elevation and electrically coupled to said first and second set of via contacts which are electrically connected to the semiconductor devices and said via contacts are spaced apart and centrally disposed along a first and second line that are parallel along the longitudinal axis, alternating via contacts in the first and second set of via contacts are interconnected respectively to a first and second surface conductors which run the length of the chip within the first and second line to form a first and second bus and said chip further having conductive pads coupled to said surface conductors, said conductive pads formed on an insulative bump on top of the layer of insulative coating material such that the pads are at an elevation different from the elevation of said surface conductors; and said chip being coupled to said substrate by means of said conductive pads being bonded to said contact elements.
Claim 3
Dependent Claim
13 words
The apparatus of claim 1, wherein said substrate is a printed circuit board.
Claim 4
Dependent Claim
11 words
The apparatus of claim 1, wherein said substrate is a ceramic.
Claim 5
Dependent Claim
17 words
The apparatus of claim 3 firer comprising an insulative material disposed between said substrate and said chip.
Claim 6
Dependent Claim
12 words
The apparatus of claim 4, wherein said insulative material is an epoxy.
Claim 7
Dependent Claim
31 words
The apparatus of claim 1 wherein said chip has a periphery defined by the chip's sides and said conductive pad is spaced away from and within the periphery of said chip.
Claim 8
Dependent Claim
14 words
The apparatus of claim 1 wherein said substrate is made of a flexible material.
Claim 9
Dependent Claim
16 words
The apparatus of claim 1 wherein said first bus provides power to said integrated circuit chip.
Claim 10
Dependent Claim
18 words
The apparatus of claim 8 wherein said second bus provides a common ground to said integrated circuit chip.
Claim 11
Dependent Claim
14 words
The apparatus of claim 9 wherein the conductive pads and surface conductors are copper.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-02-22 | 2002-08-24 | 2003-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-02-22 | 2006-08-24 | 2007-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-02-22 | 2010-08-24 | 2011-02-23 | $7700.00 | Window Closed / Lapsed |