Patent US5861676A successfully refreshed from Google Patents.
US5861676A
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Method of forming robust interconnect and contact structures in a semiconductor and/or integrated circuit
Assignee: Monterey Research LLC
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Filing: 1996-11-27
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Granted: 1999-01-19
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Expires: 2016-11-27
Abstract
Abstract A conducting trench in a dielectric layer can function as both (a) a plurality of contacts and (b) an interconnect in a semiconductor device. The conducting trench may be made by depositing a conductor in a trough formed in a dielectric layer of the device.
Inventors
- 👤 Ting Yen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:16
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; Y; Y10; Y10S; Y10S257/00; Y10S257/905
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
110 words
A method of forming an interconnect and/or contact structure in a semiconductor or integrated circuit, comprising: forming a trough in a structure comprising a semiconductor substrate, gates on said substrate, an etch stop layer on at least a first portion of said substrate, and a dielectric layer on at least a second portion of said substrate, wherein portions of said etch stop layer and a plurality of substrate regions are exposed in said trough; and depositing a conductor in said trough, thereby forming a conducting trench; wherein said conducting trench electrically connects at least two of said substrate regions, and said conducting trench contacts portions of said etch stop layer.
Claim 2
Independent Claim
110 words
A method of forming an interconnect and/or contact structure in a semiconductor or integrated circuit, comprising: forming a trough in a structure comprising a semiconductor substrate, gates on said substrate, an etch stop layer on at least a first portion of said substrate, and a dielectric layer on at least a second portion of said substrate, wherein portions of said etch stop layer and a plurality of substrate regions are exposed in said trough; and depositing a conductor in said trough, thereby forming a conducting trench; wherein said conducting trench electrically connects at least two of said substrate regions, and said conducting trench contacts portions of said etch stop layer.
Claim 3
Dependent Claim
46 words
The method of claim 1, wherein said substrate, said gates, said etch stop layer, and said dielectric layer, are prepared by a process comprising: etching a trough through said dielectric layer, thereby exposing said portions of said etch stop layer and said plurality of substrate regions.
Claim 4
Dependent Claim
36 words
The method of claim 2, wherein said process further comprises, prior to said etching of said trough: depositing said etch stop layer, followed by exposing said plurality of substrate regions by etching said etch stop layer.
Claim 5
Dependent Claim
35 words
The method of claim 2, wherein said process further comprises, prior to said etching of said trough: exposing said plurality of substrate regions by etching said etch stop layer, followed by depositing said dielectric layer.
Claim 6
Dependent Claim
20 words
The method of claim 1, wherein said dielectric layer comprises a glass, and said etch stop layer comprises a nitride.
Claim 7
Dependent Claim
17 words
The method of claim 1, wherein said gates are encapsulated with caps and spacers comprising a nitride.
Claim 8
Dependent Claim
19 words
The method of claim 6, wherein said conducting trench comprises tungsten, a tungsten alloy, aluminum or an aluminum alloy.
Claim 9
Dependent Claim
18 words
The method of claim 1, wherein said conducting trench electrically connects at least three of said substrate regions.
Claim 10
Dependent Claim
28 words
The method of claim 1, wherein said conducting trench has a minimum depth of 0.3-5 μm between two of said substrate regions electrically connected by said conducting trench.
Claim 11
Independent Claim
67 words
A method of forming an interconnect and/or contact structure in a semiconductor or integrated circuit, comprising: etching a pattern through an etch stop layer on at least a first portion of a substrate, thereby exposing a plurality of substrate regions; followed by depositing a dielectric layer on said substrate; wherein gates are on said substrate, and said etch stop layer is on a portion of said gates.
Claim 12
Independent Claim
67 words
A method of forming an interconnect and/or contact structure in a semiconductor or integrated circuit, comprising: etching a pattern through an etch stop layer on at least a first portion of a substrate, thereby exposing a plurality of substrate regions; followed by depositing a dielectric layer on said substrate; wherein gates are on said substrate, and said etch stop layer is on a portion of said gates.
Claim 13
Dependent Claim
37 words
The method of claim 10, further comprising etching a trough through a dielectric layer on at least a second portion of said substrate, thereby exposing portions of said etch stop layer and said plurality of substrate regions.
Claim 14
Dependent Claim
42 words
The method of claim 11, further comprising deposition a conductor in said trough, thereby forming a conducting trench; wherein said conducting trench electrically connects at least two of said substrate regions, and said conducting trench contacts portions of said etch stop layer.
Claim 15
Dependent Claim
28 words
The method of claim 12, wherein said conducting trench has a minimum depth of 0.3-5 μm between two of said substrate regions electrically connected by said conducting trench.
Claim 16
Dependent Claim
33 words
The method of claim 1, wherein said dielectric layer comprises a glass, said etch stop layer comprises a nitride, and said conducting trench comprises tungsten, a tungsten alloy, aluminum or an aluminum alloy.
Claim 17
Dependent Claim
63 words
A semiconductor device, comprising: (i) a substrate, (ii) gates on said substrate, (iii) an etch stop layer on at least a first portion of said substrate, (iv) a dielectric layer on at least a second portion of said substrate, and (v) a conducting trench in said dielectric layer, electrically connecting at least two substrate regions and contacting portions of said etch stop layer.
Claim 18
Dependent Claim
63 words
A semiconductor device, comprising: (i) a substrate, (ii) gates on said substrate, (iii) an etch stop layer on at least a first portion of said substrate, (iv) a dielectric layer on at least a second portion of said substrate, and (v) a conducting trench in said dielectric layer, electrically connecting at least two substrate regions and contacting portions of said etch stop layer.
Claim 19
Dependent Claim
17 words
The semiconductor device of claim 15, wherein said conducting trench electrically connects at least three substrate regions.
Claim 20
Dependent Claim
38 words
The semiconductor device of claim 15, wherein a ratio of (a) the depth of said conducting trench over one of said substrate regions to (b) the depth of said conducting trench over one of said gates, is 1:1-1:20.
Claim 21
Dependent Claim
35 words
The semiconductor device of claim 15, wherein a ratio of (a) the depth of said conducting trench over said gate to (b) the depth of insulation between said conducting trench and said gate is 1:1-1:100.
Claim 22
Dependent Claim
34 words
The semiconductor device of claim 15, wherein said dielectric layer comprises a glass, said etch stop layer comprises a nitride, and said conducting trench comprises tungsten, a tungsten alloy, aluminum or an aluminum alloy.
Claim 23
Dependent Claim
9 words
A product produced by the method of claim 1.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-18 | 2002-07-20 | 2003-01-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-18 | 2006-07-20 | 2007-01-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-18 | 2010-07-20 | 2011-01-19 | $7700.00 | Window Closed / Lapsed |