US4892835A
Expired / Lapsed
US
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Method of manufacturing a field effect transistor
Assignee: Ommic SAS
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Filing: 1988-03-23
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Granted: 1990-01-09
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Expires: 2008-03-23
Abstract
Abstract The invention relates to a method of manufacturing a field effect transistor comprising at the surface of a substrate of semi-insulating gallium arsenide W an active n-type active layer (102), on which is formed a gate electrode (G) of the Schottky type having at its lower part (15) the general form of a trapezoid, whose minor base is in contact with the active layer, then comprising on either side of the active layer a region of the n + type (101 and 101') constituting the source and drain regions, of which the edges adjacent to the active layer are self-aligned with the edges of the major base of the trapezoid, and moreover comprising source (S) and drain (D) electrodes of the ohmic contact type formed at the surface of the regions of the n + type. This transistor is characterized in that the gate electrode is composed of a weakly resistive metallic layer (105) and comprises an upper part (51) disposed on the major base of the trapezoid having a central metallic region (105) and a peripheral zone (106 ) of SiO 2 , which projects beyond the surface of the major base of the trapezoid, in that the source (S) and drain (D) electrodes (107) are self-aligned with the outer edges of the peripheral zone (106) of the gate, the latter being at right angles to a layer (103,104) of Si 3 N 4 separating the electrodes from each other.
Inventors
- 👤 Patrick D. Rabinzohn
- 👤 Christian Rocher
- 👤 Serge Gourrier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:45
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0618; H10D30/0612; H10D30/0614; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6738; H10D30/674; H10D30/675; H10D30/791; H10D30/792; H10D30/80; H10D30/87; H10D30/873; H10D64/00; H10D64/01; H10D64/012; H10D64/0124; H10D64/0125; H10D64/60; H10D64/64; H10D62/00; H10D62/80; H10D62/85; Y; Y10; Y10S; Y10S148/00; Y10S148/105
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
571 words
A method of manufacturing a field effect transistor semiconductor device comprising the steps of (a) forming a substrate of a monocrystalline semiconductor material, said substrate having a surface orientated parallel to a crystallographic plane of said semiconductor material, (b) forming a first layer of a first dielectric material at said surface, (c) forming at least one first mask on said first layer (d) etching said first layer relative to said first mask by reactive ion etching to obtain at least one first dielectric area of said first layer having a shape of said first mask, said first mask being disposed on said first dielectric area, (e) forming a second mask at a spacing around said first dielectric area to expose portions of said substrate through a first opening, (f) implanting ions into said substrate through said first opening to form source and drain regions of a first conductivity in said substrate, said source and drain regions having a first resistivity different from a resistivity of said substrate, (g) removing said second mask, (h) forming at least one second layer over each of said first layer, said source and drain regions, and said substrate, said second layer being a second dielectric material with a uniform thickness, said uniform thickness of said second layer being at least equal to a thickness of said first dielectric area, (i) planarizing the semiconductor device to said thickness of said first dielectric area to expose said first dielectric area, (j) reactive ion etching said first dielectric area down to said substrate to form at least one second opening through said second layer to said substrate, (k) implanting ions into said substrate through said second opening to form at least one active layer of said first conductivity, said active layer having a second resistivity different from said source and drain regions, (l) forming first spacers in said second opening at edges of said second layer, said first spacers being made of said second dielectric material, and said first spacers reducing dimensions of said second opening to a length L, (m) depositing gate metal layer in said at least one second opening to a thickness exceeding said second dielectric material, said gate metal layer extending over said second dielectric material at a uniform thickness, and said gate metal layer having a depression at said second opening, (n) depositing a further layer over said gate metal layer to a further uniform thickness, said further layer being selected from the group consisting of titanium (Ti) and said first dielectric material, (o) planarizing said semiconductor device down to said gate metal layer, a portion of said further layer remaining in said depression, (p) etching said gate metal layer around said portion of said further layer down to said second layer by one of selective reactive ion etching and a beam of ions of a neutral gas, said portion acting as a third mask to form at least one gate electrode having said length L, (q) forming second spacers on exposed edges of said gate electrode to form a peripheral dielectric part around said gate electrode at right angles to said second layer, said peripheral dielectric part being of said first dielectric material, and (r) etching said second layer down to said surface of said substrate to expose said source and drain regions and said substrate by selective reactive ion etching, said etching being prolonged to laterally etch under said peripheral dielectric part.
Claim 2
Independent Claim
571 words
A method of manufacturing a field effect transistor semiconductor device comprising the steps of (a) forming a substrate of a monocrystalline semiconductor material, said substrate having a surface orientated parallel to a crystallographic plane of said semiconductor material, (b) forming a first layer of a first dielectric material at said surface, (c) forming at least one first mask on said first layer (d) etching said first layer relative to said first mask by reactive ion etching to obtain at least one first dielectric area of said first layer having a shape of said first mask, said first mask being disposed on said first dielectric area, (e) forming a second mask at a spacing around said first dielectric area to expose portions of said substrate through a first opening, (f) implanting ions into said substrate through said first opening to form source and drain regions of a first conductivity in said substrate, said source and drain regions having a first resistivity different from a resistivity of said substrate, (g) removing said second mask, (h) forming at least one second layer over each of said first layer, said source and drain regions, and said substrate, said second layer being a second dielectric material with a uniform thickness, said uniform thickness of said second layer being at least equal to a thickness of said first dielectric area, (i) planarizing the semiconductor device to said thickness of said first dielectric area to expose said first dielectric area, (j) reactive ion etching said first dielectric area down to said substrate to form at least one second opening through said second layer to said substrate, (k) implanting ions into said substrate through said second opening to form at least one active layer of said first conductivity, said active layer having a second resistivity different from said source and drain regions, (l) forming first spacers in said second opening at edges of said second layer, said first spacers being made of said second dielectric material, and said first spacers reducing dimensions of said second opening to a length L, (m) depositing gate metal layer in said at least one second opening to a thickness exceeding said second dielectric material, said gate metal layer extending over said second dielectric material at a uniform thickness, and said gate metal layer having a depression at said second opening, (n) depositing a further layer over said gate metal layer to a further uniform thickness, said further layer being selected from the group consisting of titanium (Ti) and said first dielectric material, (o) planarizing said semiconductor device down to said gate metal layer, a portion of said further layer remaining in said depression, (p) etching said gate metal layer around said portion of said further layer down to said second layer by one of selective reactive ion etching and a beam of ions of a neutral gas, said portion acting as a third mask to form at least one gate electrode having said length L, (q) forming second spacers on exposed edges of said gate electrode to form a peripheral dielectric part around said gate electrode at right angles to said second layer, said peripheral dielectric part being of said first dielectric material, and (r) etching said second layer down to said surface of said substrate to expose said source and drain regions and said substrate by selective reactive ion etching, said etching being prolonged to laterally etch under said peripheral dielectric part.
Claim 3
Dependent Claim
55 words
A method according to claim 1, wherein source and drain contacts are formed by depositing on said source and drain regions a metal forming an ohmic contact with said source and drain regions, said step of depositing being carried out by using said third mask and said peripheral dielectric part to mask said gate electrode.
Claim 4
Dependent Claim
13 words
A method according to claim 2, wherein said third mask is titanium (Ti).
Claim 5
Dependent Claim
15 words
A method according to claim 2, wherein said third mask is said first dielectric material.
Claim 6
Dependent Claim
164 words
A method according to claim 1, wherein several of said first masks are formed to define several fingers and said step (d) forms several of said first dielectric areas, said several of said first dielectric areas having the shape of said several fingers, wherein said step (j) forms several of said second openings from said several fingers, and said step (k) forms several of said active layers separated by at least one region of said first conductivity and said second resistivity, wherein said step (l) forms said first spacers at edges of said several second openings, and said step (m) forms a gate metal layer at respective ones of said several second openings, and wherein said gate metal layer in said several second openings form a plurality of gate electrodes, said plurality of gate electrodes being separated by a distance equal to the sum of the thickness of said second spacers on exposed edges of respective adjacent ones of said plurality of gate electrodes.
Claim 7
Dependent Claim
55 words
A method according to claim 5, wherein source and drain contacts are formed by depositing on said source and drain regions a metal forming an ohmic contact with said source and drain regions, said step of depositing being carried out by using said third mask and said peripheral dielectric part to mask said gate electrode.
Claim 8
Dependent Claim
13 words
A method according to claim 5, wherein said third mask is titanium (Ti).
Claim 9
Dependent Claim
15 words
A method according to claim 5, wherein said third mask is said first dielectric material.
Claim 10
Dependent Claim
62 words
A method according to claim 5, wherein between step (l) and step (m), the following additional step is carried out: (l') forming a depression in said at least one active layer to locally reduce the thickness of said at least one active layer, said step of forming said depression being carried out by one of selective reactive ion etching and chemical etching.
Claim 11
Dependent Claim
62 words
A method according to claim 5, wherein between step (j) and step (k), the following additional step is carried out: (j') implanting ions of high energy into said substrate through said second opening to form a deep layer of second conductivity, and wherein said at least one active layer of said first conductivity is formed in step (k) above said deep layer.
Claim 12
Dependent Claim
154 words
A method according to claim 10, wherein said substrate is formed of semi-insulating gallium arsenide (GaAs), wherein said ions implanted in said step (f) are silicon ions implanted at a concentration of about 10 17 to 10 18 atoms per cm 3 to form said source and drain regions with a n+ conductivity, wherein said ions implanted in said step (k) are silicon ions implanted at a concentration of about 5×10 16 to 5×10 17 atoms per cm 3 to form said at least one active layer with a n conductivity, wherein said ions implanted in said step (j') are one of magnesium (mg) ions and beryllium (Be) ions implanted at a concentration of about 10 16 to 10 17 atoms per cm 3 to form said deep layer with a p conductivity, and wherein said ion implanting steps are carried out with an implantation annealing treatment at about 800° C. for 20 minutes.
Claim 13
Dependent Claim
122 words
A method according to claim 5, wherein said step (m) is carried out by depositing a superimposition of metallic layers selected from the group consisting of (i) a superimposition of tungsten (W), tantalum (Ta), and gold (Au) having thicknesses of about 200 nm, about 100 nm, and more than 500 nm, respectively; (ii) a superimposition of tungsten nitride (WN), tantalum nitride (TaN), and gold (Au) having thicknesses of about 200 nm, about 100 nm, and more than 500 nm, respectively; and (iii) a superimposition of tungsten (W) and gold (Au) having thicknesses of about 200 nm and more than 500 nm, respectively; and wherein said superimposition of multiple gate layers is formed by one of vapor deposition in vacuo and cathode sputtering.
Claim 14
Dependent Claim
87 words
A method according to claim 12, wherein after said step (r) ohmic source and drain contacts are formed by depositing a layer of a gold-germanium (Au-Ge) alloy by one of vapor deposition in vacuo and cathode sputtering on said source and drain regions, depositing a layer of nickel (Ni) by one of vapor deposition in vacuo and cathode sputtering, and heating to a temperature of about 450° C. to form a gold-germanium-nickel (Au-Ge-Ni) alloy, said Au-Ge-Ni alloy having a thickness of about 0.5 to 1 micron (μm).
Claim 15
Dependent Claim
33 words
A method according to claim 13, wherein said first dielectric material is formed of silica (SiO 2 ), and said second dielectric material is formed of silicon nitride (Si 3 N 4 ).
Claim 16
Dependent Claim
93 words
A method according to claim 14, wherein each of said layers, except said gold and silica layers, are etched by reactive ion etching using CHF 3 +SF 6 gases, wherein said gold layers are etched by a beam of ions of a neutral gas, and wherein said silica layers are etched by reactive ion etching with CHF 3 +SF 6 gases to obtain etching edges inclined to said substrate or by reactive ion etching with pure CH 3 or CF 4 gases at high pressure to obtain etching edges perpendicular to said substrate.
Claim 17
Dependent Claim
62 words
A method according to claim 1, wherein between step (l) and step (m), the following additional step is carried out: (l') forming a depression in said at least one active layer to locally reduce the thickness of said at least one active layer, said step of forming said depression being carried out by one of selective reactive ion etching and chemical etching.
Claim 18
Dependent Claim
61 words
A method according to claim 1, wherein between step (j) and step (k), the following additional step is carried out: (j') implanting ions of high energy into said substrate through said second opening to form a deep layer of second conductivity, and wherein said at least one active layer of said conductivity is formed in step (k) above said deep layer.
Claim 19
Dependent Claim
154 words
A method according to claim 17, wherein said substrate is formed of semi-insulating gallium arsenide (GaAs), wherein said ions implanted in said step (f) are silicon ions implanted at a concentration of about 10 17 to 10 18 atoms per cm 3 to form said source and drain regions with a n+ conductivity, wherein said ions implanted in said step (k) are silicon ions implanted at a concentration of about 5×10 16 to 5×10 17 atoms per cm 3 to form said at least one active layer with a n conductivity, wherein said ions implanted in said step (j') are one of magnesium (mg) ions and beryllium (Be) ions implanted at a concentration of about 10 16 to 10 17 atoms per cm 3 to form said deep layer with a p conductivity, and wherein said ion implanting steps are carried out with an implantation annealing treatment at about 800° C. for 20 minutes.
Claim 20
Dependent Claim
122 words
A method according to claim 1, wherein said step (m) is carried out by depositing a superimposition of metallic layers selected from the group consisting of (i) a superimposition of tungsten (W), tantalum (Ta), and gold (Au) having thicknesses of about 200 nm, about 100 nm, and more than 500 nm, respectively; (ii) a superimposition of tungsten nitride (WN), tantalum nitride (TaN), and gold (Au) having thicknesses of about 200 nm, about 100 nm, and more than 500 nm, respectively; and (iii) a superimposition of tungsten (W) and gold (Au) having thicknesses of about 200 nm and more than 500 nm, respectively; and wherein said superimposition of multiple gate layers is formed by one of vapor deposition in vacuo and cathode sputtering.
Claim 21
Dependent Claim
87 words
A method according to claim 19, wherein after said step (r) ohmic source and drain contacts are formed by depositing a layer of a gold-germanium (Au-Ge) alloy by one of vapor deposition in vacuo and cathode sputtering on said source and drain regions, depositing a layer of nickel (Ni) by one of vapor deposition in vacuo and cathode sputtering, and heating to a temperature of about 450° C. to form a gold-germanium-nickel (Au-Ge-Ni) alloy, said Au-Ge-Ni alloy having a thickness of about 0.5 to 1 micron (μm).
Claim 22
Dependent Claim
33 words
A method according to claim 20, wherein said first dielectric material is formed of silica (SiO 2 ), and said second dielectric material is formed of silicon nitride (Si 3 N 4 ).
Claim 23
Dependent Claim
93 words
A method according to claim 21, wherein each of said layers, except said gold and silica layers, are etched by reactive ion etching using CHF 3 +SF 6 gases, wherein said gold layers are etched by a beam of ions of a neutral gas, and wherein said silica layers are etched by reactive ion etching with CHF 3 +SF 6 gases to obtain etching edges inclined to said substrate or by reactive ion etching with pure CH 3 or CF 4 gases at high pressure to obtain etching edges perpendicular to said substrate.
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