Floating gate semiconductor device having a portion formed with a recess

Claim 2

A semiconductor device comprising: a semiconductor layer having a trench therein, said trench having a bottom, first and second sides, and in cross section comprises a "V" shape; an oxide layer having a generally uniform thickness formed over said bottom and said first and second sides; a transistor source and a transistor drain separated by said trench, said source and said drain each having a lower surface, said trench bottom being below said lower surface of at least one of said source and said drain; a transistor channel along said bottom of said trench; a floating gate at least partially within said trench; and a control gate overlying said floating gate.

Claim 3

The semiconductor device of claim 1 wherein said floating gate overlies three sides of said source and three sides of said drain.

Claim 4

The semiconductor device of claim 2 wherein said first side comprises a portion of said source and said channel, and said second side comprises a portion of said drain and said channel.

Claim 5

The semiconductor device of claim 1 wherein said bottom of said trench is below said lower surface of said source and below said lower surface of said drain.

Claim 6

The device of claim 1 wherein said semiconductor layer has a generally planar surface wherein said source and said drain are located along said planar surface.

Claim 7

The device of claim 1 wherein said trench bottom is below said lower surface of said source and said lower surface of said drain.

Claim 8

The device of claim 1 wherein said source, said drain, and said channel form part of an enhancement mode transistor.

Claim 9

The semiconductor device of claim 1 wherein said oxide extends along said bottom and said first and second sides in their entirety.

Claim 10

A memory device comprising: a semiconductor layer having a first surface and a second surface and further having a trench therein, said trench having a bottom and first and second sides and a depth of between about 3,000 Å and about 7,000 Å; a first oxide insulation layer consisting essentially of tunnel oxide having a generally uniform thickness of between about 30 Å and about 200 Å formed over said bottom and said first and second sides; a transistor source within said first surface of said semiconductor layer, said source having a lower surface, wherein a bottom of said trench extends below said lower surface of said source; a transistor drain within said second surface of said semiconductor layer, said drain having a lower surface, wherein said bottom of said trench extends below said lower surface of said drain, and wherein said trench separates said source and said drain; a transistor channel along at least said bottom of said trench; a floating gate having a thickness of between about 500 Å and about 1,500 Å formed at least partially within said trench; a control gate having a thickness of between about 1,500 Å and about 3,000 Å superjacent and overlying said floating gate; a second oxide layer having a thickness of between about 50 Å and about 100 Å interposed between said floating gate and said control gate; a nitride layer having a thickness of between about 100 Å and about 250 Å interposed between said floating gate and said control gate, wherein said first oxide layer is interposed between said trench bottom and said floating gate.

Claim 11

A memory device comprising: a semiconductor layer having a first surface and a second surface and further having a trench therein, said trench having a bottom and first and second sides and a depth of between about 3,000 Å and about 7,000 Å; a first oxide insulation layer consisting essentially of tunnel oxide having a generally uniform thickness of between about 30 Å and about 200 Å formed over said bottom and said first and second sides; a transistor source within said first surface of said semiconductor layer, said source having a lower surface, wherein a bottom of said trench extends below said lower surface of said source; a transistor drain within said second surface of said semiconductor layer, said drain having a lower surface, wherein said bottom of said trench extends below said lower surface of said drain, and wherein said trench separates said source and said drain; a transistor channel along at least said bottom of said trench; a floating gate having a thickness of between about 500 Å and about 1,500 Å formed at least partially within said trench; a control gate having a thickness of between about 1,500 Å and about 3,000 Å superjacent and overlying said floating gate; a second oxide layer having a thickness of between about 50 Å and about 100 Å interposed between said floating gate and said control gate; a nitride layer having a thickness of between about 100 Å and about 250 Å interposed between said floating gate and said control gate, wherein said first oxide layer is interposed between said trench bottom and said floating gate.

Claim 12

The memory device of claim 9 wherein in a cross section perpendicular with said floating gate across said source and drain, said control gate extends beyond first and second edges of said floating gate.

Claim 13

The memory device of claim 9 wherein said floating gate overlies at least three sides of said source and at least three sides of said drain.

Claim 14

The memory device of claim 9 wherein said first side comprises a portion of said source and a portion of said channel, and said second side comprises a portion of said drain and a portion of said channel.