Abstract Provided is a semiconductor memory device wherein nonvolatile memory elements are arranged in a matrix configuration, each of the memory elements having a field effect transistor including a floating gate, an interlayer insulating film and a control gate electrode which are stacked on an insulating film covering a semiconductor substrate, and a source region and a drain region which are respectively formed in the semiconductor substrate on both sides of the gate electrode, the floating gate, interlayer insulating film and control gate electrode being formed in a recess provided in the semiconductor substrate. The semiconductor device of such a structure is reduced in size and highly integrated with its high-performance characteristics maintained.
A semiconductor memory device comprising: a plurality of nonvolatile memory elements arranged in a matrix configuration, each of the memory elements having a field effect transistor including a floating gate, an interlayer insulating film and a control gate electrode which are sequentially stacked on an insulating film covering a semiconductor substrate; a plurality of pairs of source and drain regions respectively formed in the semiconductor substrate on both sides of the gate electrode; polysilicon lines formed on the substrate, said polysilicon lines electrically connect the source regions; and polysilicon electrodes formed on the drain regions upon which metal lines are connected, wherein the floating gate, interlayer insulating film and control gate electrode being formed in a recess provided in the semiconductor substrate.
Claim 2
Dependent Claim
122 words
A semiconductor memory device comprising: a plurality of nonvolatile memory elements arranged in a matrix configuration, each of the memory elements having a field effect transistor including a floating gate, an interlayer insulating film and a control gate electrode which are sequentially stacked on an insulating film covering a semiconductor substrate; a plurality of pairs of source and drain regions respectively formed in the semiconductor substrate on both sides of the gate electrode; polysilicon lines formed on the substrate, said polysilicon lines electrically connect the source regions; and polysilicon electrodes formed on the drain regions upon which metal lines are connected, wherein the floating gate, interlayer insulating film and control gate electrode being formed in a recess provided in the semiconductor substrate.
Claim 3
Dependent Claim
77 words
The semiconductor memory device of claim 1, further comprising a plurality of three-layered polysilicon structures, each having a first polysilicon film forming a source line, from one of the polysilicon lines, arranged vertically or transversely, a second polysilicon film forming said floating gate of each of said memory elements, and a third polysilicon film forming a word line through which the control gate electrodes of the memory elements arranged vertically or transversely are connected with one another.
Claim 4
Dependent Claim
23 words
The semiconductor memory device of claim 2, wherein said first and/or third polysilicon films are of a three-layered structure of doped polysilicon-tungsten silicide-polysilicon.