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US5852306A
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Flash memory with nanocrystalline silicon film floating gate
Assignee: Micron Technology Inc
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Filing: 1997-01-29
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Granted: 1998-12-22
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Expires: 2017-01-29
Abstract
Abstract A memory is described which has memory cells that store data using hot electron injection. The data is erased through electron tunneling. The memory cells are described as floating gate transistors wherein the floating gate is fabricated using a conductive layer of nanocrystalline silicon particles. Each nanocrystalline silicon particle has a diameter of about 10 Å to 100 Å. The nanocrystalline silicon particles are in contact such that a charge stored on the floating gate is shared between the particles. The floating gate has a reduced electron affinity to allow for data erase operations using lower voltages.
Inventors
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:48
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D30/6891; H10D30/6893; Y; Y10; Y10S; Y10S438/00; Y10S438/962; Y10S977/00; Y10S977/70; Y10S977/701; Y10S977/723; Y10S977/762; Y10S977/763
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
73 words
An integrated circuit meemory cell comprising: a transistor having a source, drain, control gate and a floating gate, the floating gate comprising a film of nanocrystalline silicon particles embedded in an insulating layer, the nanocrystalline silicon particles being in contact to form a conductive film, wherein the film of nanocrystalline silicon comprises a plurality of nanoscale silicon particles each have a general diameter in the range of about 10 Å to 100 Å.
Claim 2
Dependent Claim
73 words
An integrated circuit meemory cell comprising: a transistor having a source, drain, control gate and a floating gate, the floating gate comprising a film of nanocrystalline silicon particles embedded in an insulating layer, the nanocrystalline silicon particles being in contact to form a conductive film, wherein the film of nanocrystalline silicon comprises a plurality of nanoscale silicon particles each have a general diameter in the range of about 10 Å to 100 Å.
Claim 3
Dependent Claim
34 words
An integrated circuit memory cell comprising: a transistor having a source, drain, control gate and a floating gate, the floating gate comprising a conductive film of nanocrystalline silicon particles embedded in an insulating layer.
Claim 4
Dependent Claim
34 words
An integrated circuit memory cell comprising: a transistor having a source, drain, control gate and a floating gate, the floating gate comprising a conductive film of nanocrystalline silicon particles embedded in an insulating layer.
Claim 5
Dependent Claim
118 words
An integrated circuit field effect transistor comprising: a source region; a drain region; a conductive channel separating the source and drain regions; a floating gate comprising a conductive film of nanocrystalline silicon particles, the floating gate located adjacent the channel and separated therefrom by a first insulating layer; and a control gate located adjacent the floating gate and separated therefrom by a second insulating layer, wherein the film of nanocrystalline silicon comprises a plurality of nanoscale silicon particles each having a general diameter in the range of about 10 Å to 100 Å; wherein the first and second insulating layers are comprised of oxide and the floating gate is embedded in either the first or second insulating layer.
Claim 6
Dependent Claim
118 words
An integrated circuit field effect transistor comprising: a source region; a drain region; a conductive channel separating the source and drain regions; a floating gate comprising a conductive film of nanocrystalline silicon particles, the floating gate located adjacent the channel and separated therefrom by a first insulating layer; and a control gate located adjacent the floating gate and separated therefrom by a second insulating layer, wherein the film of nanocrystalline silicon comprises a plurality of nanoscale silicon particles each having a general diameter in the range of about 10 Å to 100 Å; wherein the first and second insulating layers are comprised of oxide and the floating gate is embedded in either the first or second insulating layer.
Claim 7
Dependent Claim
128 words
A memory device comprising: an array of memory cells, each o the memory cells comprising: a source region, a drain region coupled to a bit line, a conductive channel separating the source and drain regions, a floating gate comprising a conductive film of nanocrystalline silicon particles, the floating gate located adjacent the channel and embedded in a first insulating layer wherein the nanocrystalline silicon particles each have a general diameter in the range of about 10 Å to 100 Å, and a control gete located adjacent the floating gate and separated therefrom by a second insulating layer, the control gate is coupled to a word line; addressing circuitry for addressing the array of memory cells; and control circuitry for controlling read and write operations of the memory device.
Claim 8
Dependent Claim
128 words
A memory device comprising: an array of memory cells, each o the memory cells comprising: a source region, a drain region coupled to a bit line, a conductive channel separating the source and drain regions, a floating gate comprising a conductive film of nanocrystalline silicon particles, the floating gate located adjacent the channel and embedded in a first insulating layer wherein the nanocrystalline silicon particles each have a general diameter in the range of about 10 Å to 100 Å, and a control gete located adjacent the floating gate and separated therefrom by a second insulating layer, the control gate is coupled to a word line; addressing circuitry for addressing the array of memory cells; and control circuitry for controlling read and write operations of the memory device.
Claim 9
Dependent Claim
14 words
The memory device of claim 4, wherein the memory device is a flash memory.
Claim 10
Dependent Claim
117 words
A memoory device comprising: an array of memory cells, each of the memory cells comprising: a source region, a drain region coupled to a bit line, a conductive channel separating the source and drain regions, a floating gate comprising a conductive film of nanocrystalline silicon particles embedded in a first layer of insulating material, wherein the nanocrystallin silicon particles each have a general diameter in the range of about 10 Å to 100 Å, and a control gate located adjacent the floating gate and separated therefrom, the control gate is coupled to a word line; addressing circuitry for addressing the array of memory cells; and control circuitry for controlling read and write operations of the memory device.
Claim 11
Dependent Claim
117 words
A memoory device comprising: an array of memory cells, each of the memory cells comprising: a source region, a drain region coupled to a bit line, a conductive channel separating the source and drain regions, a floating gate comprising a conductive film of nanocrystalline silicon particles embedded in a first layer of insulating material, wherein the nanocrystallin silicon particles each have a general diameter in the range of about 10 Å to 100 Å, and a control gate located adjacent the floating gate and separated therefrom, the control gate is coupled to a word line; addressing circuitry for addressing the array of memory cells; and control circuitry for controlling read and write operations of the memory device.
Claim 12
Dependent Claim
84 words
A non-volatile cell comprising: a transistor having a source, drain, control gate and a floating gate, the floating gate comprising a film of nanocrystalline silicon particles embedded in an insulating layer and in contact to form a conductive film, wherein the film of nanocrystalline silicon comprises a plurality of nanoscale silicon particles each have a general diameter in the range of about 10 Å to 100 Å such that the floating gate has a low electron affinity to allow for low voltage erase operations.
Claim 13
Dependent Claim
84 words
A non-volatile cell comprising: a transistor having a source, drain, control gate and a floating gate, the floating gate comprising a film of nanocrystalline silicon particles embedded in an insulating layer and in contact to form a conductive film, wherein the film of nanocrystalline silicon comprises a plurality of nanoscale silicon particles each have a general diameter in the range of about 10 Å to 100 Å such that the floating gate has a low electron affinity to allow for low voltage erase operations.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-21 | 2002-06-22 | 2002-12-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-21 | 2006-06-22 | 2006-12-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-21 | 2010-06-22 | 2010-12-22 | $7700.00 | Window Closed / Lapsed |