PMOS flash EEPROM cell with single poly

Abstract

Abstract A P-channel single-poly EPROM cell has P+ source and P+ drain regions, and a channel extending therebetween, formed in an N-type well. A thin layer of tunnel oxide is provided over the channel and, in some embodiments, over significant portions of P+ source and P+ drain regions. A poly-silicon floating gate overlies the tunnel oxide. A P diffusion region is formed in a portion of the N-well underlying the floating gate and is thereby capacitively coupled to the floating gate. In this manner, the P diffusion region serves as a control gate for the memory cell. Programming is accomplished by coupling a sufficient voltage to the floating gate via the control gate while biasing the source and drain regions to cause the hot injection of electrons from the N-well/drain junction to the floating gate, while erasing is realized by biasing the floating gate, N-well, source and drain regions appropriately so as cause the tunneling of electrons from the floating gate to the N-well, the source, and the drain. In another embodiment, an N-type diffusion region is formed within the P diffusion region and serves as the control gate.

Inventors

• 👤 Shang-De Ted Chang
• 👤 Jayson Giai Trinh

Bibliographic Details