Erasable floating gate device

Claim 2

A SEMICONDUCTOR STORAGE DEVICE COMPRISING: A SUBSTRATE OF A FIRST CONDUCTIVITY TYPE; A FIRST AND SECOND SPACED-APART REGION IN SAID SUBSTRATE OF A SECOND CONDUCTIVIITY TYPE TO SAID FIRST CONDUCTIVITY TYPE, SAID REGIONS DEFINING A CHANNEL; A THIRD REGION IN SAID SUBSTRATE OF SAID FIRST CONDUCTIVITY TYPE TYPE SPACED APART FROM SAID CHANNEL; A FLOATING GATE DISPOSED ABOVE SAID CHANNEL AND EXTENDING AT LEAST TO SAID THIRD REGION; INSULATION MEANS INSULATING SAID FLOATING GATE FROM SAID SUBSTRATE AND SURROUNDING SAID FLOATING GATE; AND CONTACT MEANS, COUPLED TO SAID THIRD REGION FOR PERMITTING THE APPLICATION OF AN ELECTRICAL SIGNAL TO SAID REGION; WHEREBY CHARGE MAY BE TRANSFERRED ONTO SAID FLOATING GATE BY AVALANCHE INJECTION FROM SAID SUBSTRATE AND REMOVED FROM SAID FLOATING GATE THOUGH SAID THIRD REGION.

Claim 3

The device defined by claim 1 wherein said substrate comprises an N-type silicon.

Claim 4

The device defined by claim 2 wherein said floating gate comprises silicon.

Claim 5

The device defined by claim 2, wherein said insulation between said substrate and said floating gate is between 300-600 A thick.

Claim 6

The device defined by claim 3 wherein said insluation means between said channel and said floating gate is thicker than said insulation means between said third region and said floating gate.

Claim 7

The device defined by claim 5 wherein said insulation means between said channel and said floating gate is approximately at least 1,000 A thick.

Claim 8

A semiconductor device comprising: a substrate of a first conductivity type; a first, second and third spaced-apart regions in said substrate of a second conductivity type, said first and second regions defining a channel; a floating gate disposed above said channel and extending laterally to said third regions; insulation means completely surrounding said floating gate; and contact means coupled to said first, second and third spaced-apart regions for the slelctive application of signals to said regions; whereby the application of a voltage between said first and second regions charge may be transferred by avalanche injection onto said floating gate and charge may be removed from said floating gate by the application of a voltage between at least one of said first and second regions and said third regions.

Claim 9

A semiconductor device comprising: a substrate of a first conductivity type; a first, second and third spaced-apart regions in said substrate of a second conductivity type, said first and second regions defining a channel; a floating gate disposed above said channel and extending laterally to said third regions; insulation means completely surrounding said floating gate; and contact means coupled to said first, second and third spaced-apart regions for the slelctive application of signals to said regions; whereby the application of a voltage between said first and second regions charge may be transferred by avalanche injection onto said floating gate and charge may be removed from said floating gate by the application of a voltage between at least one of said first and second regions and said third regions.

Claim 10

the device defined by claim 7 wherein said substrate comprises N-type silicon and said floating gate comprises a P-type silicon.

Claim 11

The device defined by claim 8 wherein the quantity Beta is equal to or greater than approximately 0.5 where

Claim 12

A semiconductor storage device comprising: an N-type silicon substrate; a P-type spaced-apart source and drain regions disposed in said substrate, said source and drain regions defining a channel; a third P-type region disposed in said substrate and spaced apart from said channel; a P-type polycrystalline silicon gate disposed above said channel and extending to said third P-type region; a first silicon oxide insulative means separating said channel from said floating gate; a second silicon oxide insulation means separating said third P-type region from said floating gate; and contact means coupled to said third region for applying an electrical signal to said third region; whereby charge may be transferred and removed from saiD floating gate by the application of voltages between said first, second and third regions.

Claim 13

A semiconductor storage device comprising: an N-type silicon substrate; a P-type spaced-apart source and drain regions disposed in said substrate, said source and drain regions defining a channel; a third P-type region disposed in said substrate and spaced apart from said channel; a P-type polycrystalline silicon gate disposed above said channel and extending to said third P-type region; a first silicon oxide insulative means separating said channel from said floating gate; a second silicon oxide insulation means separating said third P-type region from said floating gate; and contact means coupled to said third region for applying an electrical signal to said third region; whereby charge may be transferred and removed from saiD floating gate by the application of voltages between said first, second and third regions.

Claim 14

The device defined in claim 10 wherein said first insulation means is thicker than said second insulation means.

Claim 15

The device defined in claim 11 wherein said first insulative means is approximately at least 1,000 A thick and said second insulation means is approximately between 200-500 A thick.

Claim 16

The device defined in claim 11 including third insulation means between said floating gate and the region of said substrate between said channel and said third region and wherein said third insulation means is thicker than said first insulation means.

Claim 17

The device defined in claim 13 wherein said third insulation means is at least 10,000 A thick.